I’ve just found another issue while using GPIO pins from Cortex-M of Verdin iMX8M-Plus running Torizon OS 6.8.0.
I think it’s another mis-configuration of device tree, but it’s not clear to me if I can get the usage I need.
I need to use two pins GPIO3_IO16 (SODIMM_64) and GPIO3_IO22 (SODIMM_32) as general purpose inputs.
But this doesn’t work, and even if I apply low or high voltage to the pin, I always read “low”.
I suspect the pin configurations is done in different way from some other node in .dts files.
I looked in the tree, but I can’t find which is the reason for this.
Looking to the datasheet I see that:
-
GPIO3_IO16 can be used as peripheral function pin for:
- I2C3 - but I disabled this node. But
pinctrl_flexspi0node is configured inimx8mp-verdin.dtsi. Should I delete this node too if I don’t need I2C3? - USDHC3 - I understand this is used on the module to connect the EMMC (so I don’t think I can disable it)
- NAND - it’s disabled in
imx8mp.dtsi
- I2C3 - but I disabled this node. But
-
GPIO3_IO22 can be used as peripheral function pin for:
- SAI5 - it’s disabled in
imx8mp.dtsi - SAI1 - it’s disabled in
imx8mp.dtsi, butpinctrl_sai1node is configured inimx8mp-verdin.dtsi. Should I delete this node too if I don’t need SAI1? - PDM - not configured in Toradex dts files
- CAN1 - it’s disabled, and moreover
pinctrl_flexcan1node doesn’t refer toSODIMM_32
- SAI5 - it’s disabled in
So, basically the question is:
are pinctrl_flexspi0 and pinctrl_sai1 responsible to the mis-configuration of the two pins (even if I2C3 and CAN1 are disabled)?
Because in imx8mp-verdin.dtsi I see
&iomuxc {
pinctrl_flexspi0: flexspi0grp {
fsl,pins =
<MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
<MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */
<MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */
<MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */
<MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */
<MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */
<MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */
<MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */
};
pinctrl_sai1: sai1grp {
fsl,pins =
<MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */
<MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */
<MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */
<MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */
<MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */
};
};
And I see that both SODIMM 64 and SODIMM 32 are configured in the iomuxc as peripheral function.
