Verdin IMX8MP and KSZ8873

Hello,
I have ethernet switch KSZ8873RLLI connected via RMII to Verdin IMX8MP.
What is needed to be configured at all?

I have in U-Boot:

  • in DTS changed MDIO address from 7 to 2
  • disabled RGMII TX clk output (I need TX CLK input, KSZ is output)

In u-boot i see eth interface on MDIO:
Net: eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]

Verdin iMX8MP # mdio list
FEC1:
2 - Generic PHY <--> ethernet@30be0000
ethernet@30bf0000:

In linux kernel:

  • changed DTS changed MDIO address from 7 to 2
/* Verdin ETH_2_RGMII */
&fec {
	fsl,magic-packet;
	phy-handle = <&ethphy1>;
	phy-mode = "mii";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_fec>;
	pinctrl-1 = <&pinctrl_fec_sleep>;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			interrupt-parent = <&gpio4>;
			interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
			micrel,led-mode = <0>;
			eee-broken-1000t;
			reg = <2>;
			refclk_in;
		};
	};
};

Nothing abou FEC or second ethernet found in dmesg or kernel messages.
What steps are needed to have KSZ8873 working?

Thanks

Hi @msv_zitnik,

Thanks for reaching out.

I assume you are using your own carrier board am I right?

Can you maybe share a snippet of the schematic on how the phy is connected?

Best Regards
Kevin

Hi @kevin.tx,

yes, we have our own carrier board. This is our RMII connection:


Hi @msv_hofmann,

can you share the the whole ethernet part also the connector?
best regards,

Matthias

Hi, @matthias.tx,
the KSZ8873 switch has two 100BASE-TX ports (names PORT 1 and PORT 2) and one RMII port (name PORT 3). Because in our carrier board, the PORT 1 and PORT 2 are not solved with regular RJ-45 connectors (the connections are solved with DIN 41612 connector to other cards in rack), the schematic of PORT 1 and PORT 2 is quite irrelevant.

However I made a test of PORTS 1 & 2 connectivity & status:

  1. Our carrier board was powered on and the Verdin booting was stopped in bootloader by sending spaces to the terminal.
  2. With our custom cables I connected the company LAN to PORT 1 and my laptop to PORT 2. I also disabled Wi-Fi in my laptop and checked, that I am connected only with the cable trough KSZ8873 eth switch on our carrier board.
  3. I am sending this post connected as described above, the LINK/ACT LEDs of KSZ8873 on the carrier boad are blinking.
  4. With Verdin terminal I checked the state of MDIO registers:
Verdin iMX8MP # mii device FEC1
Verdin iMX8MP # mii read 1 0
3100
Verdin iMX8MP # mii read 1 1
782C
Verdin iMX8MP # mii read 2 0
2020
Verdin iMX8MP # mii read 2 1
780C

So MDIO (MIIM) interface is working and according to the registers the PORT 1 & 2 links are both ON. You can check the status in the KSZ8873 datasheet, pages 39, 40. What is not working is only PORT 3 connection between KSZ8873 and Verdin, which is realized by RMII.

Note:
In the previous schematic the ref. 50MHz clock was provided from KSZ to Verdin. We slightely changed the connection, so now the ref. 50MHz clock is provided from Verdin. So R108 was removed and the ref. 50 MHz was also connected to X1 (pin 17). The XTAL1 was removed. Also few strapping resistors had to be modified. The test described above was made with this changed connection (CLK sourced from Verdin).

The information about Linux configuration can provide my SW colleague @msv_zitnik.

Q1: Both variants of the 50 MHz clock sourcing are acceptable for us so please let us know, which variant is better from the compatibility point of view. From the EMC point of view, the variant with Verding sourcing ref. 50 MHz clock is better because the lack of noisy 25 MHz clock genetaror.

Today We made measurement of RMII interface with logic analyzer.

50 MHz ref. clock is sourced by Verdin.

Ping attempt from external laptop connected to PORT 1:
The CRS, RX0 and RX1 signals from KSZ8873 to Verdin looks good from my point of view. The data signals are changed with rising edge of REF CLK and probably should be sampled by Verdin with falling edge of REF CLK. There is just one bit per clock cycle. There is something bad happenning on signals TXEN and TX0.


ARP attempt to get IP from external DHCP initiated from Verdin:
Something which looks like data appears on TX1, however there is “inverted 50 MHz clock with duty cycle > 0,5” on TX0 and TXEN, which definitely should not be there. The data on TX1 also has much lower frequency than REF CLK.


It seems Verdin ignores recieved data on CRS, RX0 and RX1, because there is no reply. Also the data on TXEN, TX0 and TX1 are totally different, then it should look like.

TX0 and TXEN signals are high-Z in Verdin, so 50 MHz ref. CLK is somehow coupled to them. I checked them with osciloscope and there is something like 0,7 V on them, so the logic analyzer was picking the noise.

Why are TX0 and TXEN set to high-Z and not to OUT to drive the signals?

hi @msv_hofmann,

you need to connect ETH_2_RGMII_MDC and ETH_2_RGMII_MDIO to be able to access the registries of the switch. What you get from the mii command on Uboot are is most likely from the on-module Phy for the first ethernet. I also can find FEC1 with my Verdin iMX8MP on Yavia Board (which only has 1 Ethernet).

I am supporting @KDehren on this thread. Feel free to follow.

@matthias.tx can continue to support you if you need more help on the hardware side.