Verdin AM62: Main SPI Performance delay

[HMUser]

Hi Team,

We have an adc interfaced at main SPI2, which provides data in time-synchronous manner. So, we have to perform 14 frames read operation(Each frame is 32 bit data) within 200us. Below is the code snippet used to perform frame read operation

memset(st->frame_data, 0x00, st->frame_size);

memset(&xfer, 0, sizeof(xfer));

xfer.tx_buf = st->frame_data;

xfer.rx_buf = st->frame_data;

xfer.len = st->frame_size;

xfer.bits_per_word = 8;

// xfer.len = (st->frame_size)/4;

// xfer.bits_per_word = 32;

// mutex_lock(&st->lock);

spi_message_init(&msg);

spi_message_add_tail(&xfer, &msg);

ret = spi_sync(st->spi, &msg);

When we probe the signals we see that there is an inconsistent behavior in SPI inter-byte transfer. The delay sometime goes upto 90-100us, which is a problem for us. The SPI clock is chosen as 10 MHz.

Request you to look into the issue and provide us a suggestion.

Solutions Tried so far-

1. We have enabled the DMA as per TI’s suggestion - https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1356551/faq-am6x-optimizing-spi-transfer-inter-byte-gaps-using-the-dma-in-linux

But, we don’t see much improvements. The inter-byte SPI transfer delay is around 2us in working case. As we keep the system for 2-3 mins the SPI transfer delay will gradually increases and thus causes the adas to go out-of sync.

2. Increase the number of bits per SPI transfer – The number of bits per word were increased to 32 instead of 8 to improve the SPI inter-byte latency. We see some improvement. However, again after sometime of SPI data capture, the system will starts introducing delay starting from executing the IIO ISR handler, SPI CS to SPI CLk delay, SPI frame to frame read delay.

Working Scenario
Operation	Delay
IIO ISR handler	16us
SPI CS to SPI CLK	5us
SPI frame to SPI frame read	9us

Non-Working Scenario
Operation	Delay
IIO ISR handler	80us
SPI CS to SPI CLK	20us
SPI frame to SPI frame read	100us

We would like to know the reason for this inconsistent delay, which happens at randomly during SPI data capture.

Looking forward for your response.

Thanks and Regards,
Akshay

[ToradexAI]

Hi, I’m the Toradex AI Assistant. The Toradex Support team will follow up with you shortly!

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Based on the context provided, I don’t have specific information about the Verdin AM62’s SPI performance issues or detailed troubleshooting steps for the described problem. However, I can offer some general suggestions that might help address the SPI performance delay:

1. Check CPU Load and Interrupt Handling: High CPU load or inefficient interrupt handling can cause delays. Ensure that the CPU is not overloaded and that the interrupt service routines (ISRs) are optimized for minimal execution time.

2. Real-Time Configuration: If your application requires strict timing, consider using a real-time kernel or configuring the system for real-time performance to reduce latency.

3. SPI Driver and Configuration: Verify that the SPI driver is configured correctly. Check for any known issues or updates related to the SPI driver for the Verdin AM62.

4. DMA Configuration: Since you have already tried enabling DMA, ensure that the DMA configuration is optimal. Sometimes, tweaking DMA settings can help improve performance.

5. Thermal and Power Management: Ensure that the system is not throttling due to thermal or power management settings, which can introduce delays.

6. Kernel and System Logs: Check kernel and system logs for any warnings or errors that might indicate underlying issues affecting SPI performance.

7. Consult TI Resources: Since the Verdin AM62 is based on a TI processor, consulting TI’s resources and forums for similar issues might provide additional insights or solutions.

If these suggestions do not resolve the issue, it may be beneficial to reach out to Toradex support or the community for more specific guidance related to the Verdin AM62 module.

Please, also check if these links can help you solve your problem:

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