Some GPIO not responding to gpiod commands

Technical Support
, , ,
1

I’m testing out my custom board (based off of the Mallow) and some of the GPIO are not responding to gpiod commands.

  1. I first start up a docker container, and give access to all the GPIO banks
    docker run --rm -it -v /dev:/dev --device /dev/gpiochip0 --device /dev/gpiochip1 --device /dev/gpiochip2 --device /dev/gpiochip3 --device /dev/gpiochip4 --device-cgroup-rule=‘c 254:* rmw’ torizonextras/arm64v8-gpiod

  2. I want set and clear " line 12: “SODIMM_221” I use gpioinfo and see its “gpiochip3” line 12

  3. I try gpioset 3 12=1 (does not set my line)

  4. I try another GPIO gpioset 0 0=1 (this sets “SODIMM_206” like it should)

  5. I try gpioset 0 0=0 ((this clears “SODIMM_206” like it should).

  6. I go back and try gpioset 3 12=1 (does NOT set my line)

the gpio shows it is an output.

Is there an overlay issue here?

2

Hi, I’m the Toradex AI Assistant. The Toradex Support team will follow up with you shortly!

Did you like my answer?

:+1: :-1:

Based on the context provided, it seems like you are experiencing issues with setting a specific GPIO line using gpiod commands on your custom board. Here are a few potential reasons and steps to troubleshoot the issue:

  1. Device Tree Configuration: Ensure that the GPIO pin you are trying to control is correctly configured in the device tree. If the pin is not muxed as a GPIO in the device tree, it will not function as expected. You may need to create or modify a device tree overlay to ensure the pin is set up correctly.

  2. Pin Multiplexing: Verify that the pin is not being used by another function or peripheral. If the pin is multiplexed with another function, it may not be available as a GPIO. Check the pin’s configuration in the device tree and ensure it is set to GPIO mode.

  3. Hardware Connections: Double-check the hardware connections on your custom board. Ensure that the pin is correctly connected and there are no hardware issues preventing it from functioning as a GPIO.

  4. Permissions and Access: Make sure that the Docker container has the necessary permissions to access the GPIO lines. You have already provided access to the GPIO banks, but ensure that there are no additional permission issues.

  5. Kernel Configuration: Check if the kernel configuration includes support for the GPIO you are trying to use. The CONFIG_POWER_RESET_GPIO or similar configurations might be necessary depending on your specific use case.

If these steps do not resolve the issue, it might be helpful to review the device tree and kernel configuration in more detail or consult with Toradex support for further assistance.

Please, also check if these links can help you solve your problem:

Device Tree Customization/ Device Tree Overlays to Enable/multiplex GPIO.

3

I did check the device tree and it calls the line out and
gpioinfo gives me

line 12: “SODIMM_221” unused output active-high

So, this tells me it’s available.

It’s weird, it seems like it should be a no brainer, but some of these GPIOs just don’t want to respond.

4

Little update here:

I hopped back on the Mallow board to try some things out. I tried to toggle the CAN_1_TX line and that didn’t work either.

Looking in the imx8mp-verdin.dtsi, it’s mapped to pinctrl_flexcan1 which goes to line 220 in the document. But it says it’s disabled.

I thought when the module…like CAN is disabled, you get your pins back. Am I wrong?

If I am how would I get the CAN pin back with an overlay? I’m assuming my issue is ever though the gpiod says it’s not used, that may not be the case. So, I need to gain control of the pins after the fact with an overlay.

5

In our version of device tree pin 221 is muxed for the RGMII_TD0 function and thus can not be used as a regular GPIO.
Could you please specify which exactly Torizon image you are using?

6

I’m using Torizon 6 (something) Can I view that in terminal some how.

I need pin 203. Which has the same issue of not responding. In the Pinout Designer tool it shows no conflicts and its ALT5 - GPIO4_IO7 -203(SAI1_RXD5). and 221 says ALT5 - GPIO4_IO12 -203(SAI1_TXD0), with no conflicts. I have a tone of GPIO that when I used the pinout designed and it said no conflicts, it was ok to use. It seems like I just have to configure the pin for it’s Alternate.

FYI
RGMII (Eth 2) is not on the Mallow Board.

7

The pinout designer shows the possibility of using a pin as a GPIO (or any other function). The actual functionality is defined by the device tree. If a pin is not muxed as a GPIO, you cannot use it as a GPIO, regardless of the carrier board you are using.

You need to modify your device tree and rebuild it. You can also use Torizon Core Builder for this.

8

I was leaning doing an overlay to reconfigure, instead of rebuilding the device tree

I think as long as the modules that use the GPIO is disabled, I think I should be able to add the pin control to an overlay. Like below sets the that CAN1 TX back to a GPIO.

pinctrl_sample: gpioSamplegrp {
	fsl,pins = <
		MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03		0x184	/* SODIMM 206 */
	>;
};

I believe all my pins are muxed. I’m looking at the -pinfun.h file. Alos I see most of them in the ```
&iomuxc section of the device tree

9

Some progress, but still need help.

I managed to use the Mallow board as a test and reconfigured the CAN_TX to is responds to a gpioset command. I used an overlay to do this.
polar.dts (604 Bytes)

I did the same process to get make my custom board IO respond to gpioset command, but it still does not work
polardelight-overlay.dts (4.5 KB)

For example one of pin is MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 and this also has a map to &fec. if you notice in the overlay I set that module to be disabled. As I understand when the module is disabled, it frees up the pins. Any ideas on how to get this to work? I think I’m on the right track,

fragment@2 {
target = <&fec>;
overlay { status = “disabled”; };
};

10

Update-

I’m a doof - I had a misspelling for my overlay in the overlays.txt file.

It all work now!

11

I’m glad to hear that your problem has been resolved.