Pinmuxing iMX8DX for gpio-keys

Technical Support
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1

Hi! I am using a iMX8DX Colibri SoM with an Iris V2 board. I want to set up a set of pins as gpio-keys. I could handle 4 of them but I’m having troubles setting up 2 more. For the sake of brevity I’m leaving out from the examples the pins that did work.

I have tried and failed with UART0_RX (SODIMM 36), UART0_TX (SODIMM 38), SPI2_SCK (SODIMM 88), SPI2_CS0 (SODIMM 86). Ideally I would use the first two, so here I’ll explain what I did for them.

First of all UART0_TX and UART0_RX are part of the pinctrl_lpuart0, so I disabled lpuart0:

&lpuart0 {
	status = "disabled";
};

And then configured them as gpio-keys:

/ {
	model = "Toradex Colibri iMX8DX on Colibri Iris V2 Board, my own changes";
	compatible = "toradex,colibri-imx8x-iris-v2",
		     "toradex,colibri-imx8x",
		     "fsl,imx8qxp", "fsl,imx8dx";

	/* gpio-keys */
	gpio-keys-2 {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpiokeys_2>;

		right_key {
			label = "Right-key";
			gpios = <&lsio_gpio1 21 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
			linux,code = <KEY_RIGHT>;
			debounce-interval = <10>;
		};

		down_key {
			label = "Left-key";
			gpios = <&lsio_gpio1 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
			linux,code = <KEY_LEFT>;
			debounce-interval = <10>;
		};
	};
};

&iomuxc {
	pinctrl_gpiokeys_2: gpiokeysgrp2 {
		fsl,pins = <
			IMX8QXP_UART0_RX_LSIO_GPIO1_IO21	0x26000020	/* SODIMM  36, right key */
			IMX8QXP_UART0_TX_LSIO_GPIO1_IO22	0x26000020	/* SODIMM  38, left key */
		>;
	};
};

The pinmuxing value I took it from NXP’s IMX8DQXPRM.pdf aka “i.MX 8DualX/… Applications Processor Reference Manual”

In this case:
Bits 29 to 27: 100b aka LSIO_GPIO1_IO21
Bits 26-25: 11b aka INOUT
Bits 6-5: 01b aka pull up.

Once the dtb is compiled and loaded I can see that:

SODIMM 36 aka iris v2’s X16 pin 31 is at 3.2V
SODIMM 38 aka iris v2’s X16 pin 32 is at GND.

And showkeys won’t see any changes if I put the to GND.

The same exercise can be done with SPI2_[SCK CS0 RXD TXD] pins.

What am I missing here?

2

Hi @lisandropm,

I apologize for the delay.

Can you see any errors or something related to your issue on the dmesg log?

Best Regards,
Hiago.

3

Hi @hfranco.tx ,

No need to apologize.

I have found out two things:

  1. This one is my bad: I should have turned off the MAX3243 serial driver/receiver, to which the UART lines are connected to in the Iris v2 board. I have done so by removing SODIMM 104 as a GPIO and:
&lsio_gpio3 {
	gpio-line-names = "SODIMM_96",
[snip reduced list of GPIO names]
		  "SODIMM_106";
	status = "okay";

/* Turn off the UART serial driver/receiver */
	uart_off {
		gpio-hog;
		gpios = <23 0>;
		output-low;
	};
};

With this both lines seems now to be on GND.

The other thing I missed from dmesg is the following message, which I still can’t fully understand:

imx8qxp-pinctrl scu:pinctrl: no groups defined in /scu/pinctrl/gpiokeysgrp2

Any ideas?

4

For the sake of completeness I have also tried enabling all the SPI pins as GPIOs with a pull up.

/* Free up the SPI 
&lpspi2 {
	status = "disabled";
};

&iomuxc {
	/delete-node/ pinctrl_lpspi2;

	pinctrl_gpiokeys_2: gpiokeysgrp2 {
		fsl,pins = <
			IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03	0x06000020 /* SODIMM  88 */
			IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02	0x06000020 /* SODIMM  90 */
			IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00	0x06000020 /* SODIMM  86 */
			IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01	0x06000020 /* SODIMM  92 */
		>;
	};
};

pinctrl_gpiokeys_2 being referenced as in the original post. And even this won’t make the GPIOs be pulled up.

In all the cases so far I decompiled the dts and compared it against the default iris v2 one and the changes are there.

5

@hfranco.tx Maybe I am seeing something like this issue?

6

So X16’s pin 32 aka SODIMM 38 aka UART_B_TXD came to life once I added an external pull up of 10kOhm. Sadly that did not happen with X16’s pin 31 aka SODIMM 36 aka USART_B_RXD…

7

Hi @lisandropm,

Just to check some basics (sorry if you already did that), have you included <dt-bindings/pinctrl/pads-imx8qxp.h> to your overlay?

Can you also try with a different pin to see if you get the same error? For example, try with pins that are being used as default GPIOs.

Best Regards,
Hiago.

8

Yes, I based my dts on the imx8dx-colibri-iris-v2.dts, copying it and building from there. So all the includes should be there.

And yes, I used all the available GPIOs on the Iris v2’s X16 connector without any kind of issues. My client happens to need two more.

I just checked that the pins I have tested, at least according to public-documentation_technical-datasheets_colibri_arm_som_imx8x_datasheet.pdf aka “Colibri IMX8X Datasheet” are not marked as having a level shifter, so I’m really confused. Except I managed to screw those pins in some way I see no way in which this can’t be working without an external Pull-up (or not working at all like SODIMM 36 aka USART_B_RXD).

9

Hi @lisandropm,

I also check the schematics and there are no pull-ups or pull-downs on these pins. The only thing that might cause something is that these pins go to R4OUT and R5OUT from MAX3243.

image

Can you share the overlay or device tree that you are customizing with me?
You can use this link to upload the files and then send me the link so I can download it here: share.toradex.com.

If you don’t want to post it here (because this thread is public), you can send me a private message with the link by clink on my profile and selecting “message”.

Best Regards,
Hiago.

10

Hi @lisandropm,

Thanks for sharing the device tree.

Looking at the source code, I couldn’t see any mistakes that might be causing this issue. So I would like to recommend another test, if possible:

If I understand all correctly, the issue is the initial state of the pin, correct?

It’s possible to set the state of the pin using u-boot commands:

> gpio get
> gpio set

And the pin numbering can be checked here: GPIO Alphanumeric to GPIO Numeric Assignment | Toradex Developer Center

Can you test if you can set these pins in u-boot ?

Best Regards,
Hiago.

11

I will do right now. On the other hand I am also suffering Colibri iMX8DX: display artifacts when using GPU in the exact same way… I wonder if they are related.

12

Actually pull-up should be appearing and it does not on SODIMM 88. On SODIMM 36 nothing happens (ie, I can’t make it work).

Here are the results.

I first checked SODIMM 98, which is a GPIO in the device tree and worked out of the box as GPIO-key. I setted and cleared it without issues.

Then I did the same thing with SODIMM 88. I think I can’t configure a pull up from u-boot (which is what it is failing in that pin), so I just tested setting and clearing it, and worked as expected.

Next I checked the states of SODIMM 36 and 38, one was in and and the other one in VCC. Before proceeding I cleared SODIMM 104 in order to disable the MAX serial controller. At that point both SODIMM 36 and 38 became GND.

Finally I toggled SODIMMs 36 and 38. 36 failed, 38 did work.

So this all matches my experience in Linux, barred that I *think I can’t set up a pull up from u-boot.

13

Hi @lisandropm,

Thanks for your patience, I’m still trying to create a workaround for this issue. I wasn’t successful yet.

Can you please confirm you are still using imx8dx-colibri-iris-v2-mb.dts? The SODIMM 36 is not defined in this file.

&iomuxc {
	pinctrl_gpiokeys_2: gpiokeysgrp2 {
		fsl,pins = <
			IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21	0x20	/* SODIMM  98, up key */
			IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04	0x20	/* SODIMM  133, left key */
			IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28	0x20	/* SODIMM  101, enter key */
			IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03	0x06000020	/* SODIMM  85, F12/Settings key */
			IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03	0x06000020	/* SODIMM  88, right key */
			IMX8QXP_UART0_TX_LSIO_GPIO1_IO22	0x06000020	/* SODIMM  38, down key */
		>;
	};

Best Regards,
Hiago.

14

Hi!

I’m using the device tree I privately shared with you, which I copied and modified from imx8dx-colibri-iris-v2.dts, without the “-mb”.

Also we did test this with 3 other SoMs: same result.