IMX8M Plus SOM with Verdin Development board: Mclk not generated on MiPi-CSI Interface

Technical Support
1

Hi Toradex team,

I am facing issue Mclk is not generated on my board . The node has been added to the mainline DTS file as shown

&i2c3 {
        clock-frequency = <400000>;
        pinctrl-names = “default”;
        pinctrl-0 = <&pinctrl_i2c3>;
        status = “okay”;

os05b10: os05b10@36 {
                compatible = “ovti,os05b10”;
                reg = <0x36>;
                pinctrl-names = “default”;
                pinctrl-0 = <&pinctrl_gpio_hog3>, <&pinctrl_gpio5>;
                assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
                assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
                assigned-clock-rates = <24000000>;
                clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
                clock-names = “xclk”;
                mclk = <24000000>;
                mclk_source = <0>;
                csi_id = <0>;
                reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
                status = “okay”;

avdd-supply = <&os05b10_avdd_2v8>;
                dvdd-supply = <&os05b10_dvdd_1v2>;
                dovdd-supply = <&os05b10_dovdd_1v8>;

port {
                        os05b10_mipi_0_ep: endpoint {
                                remote-endpoint = <&mipi_csi0_ep>;
                                data-lanes = <1 2 4>;
                                clock-lanes = <0>;
                                clock-noncontinuous;
                                link-frequencies = /bits/ 64 <720000000>;

};
                };
        };
};

&mipi_csi_0 {
        #address-cells = <1>;
        #size-cells = <0>;
        status = “okay”;

port@0 {
                reg = <0>;
                mipi_csi0_ep: endpoint {
                remote-endpoint = <&os05b10_mipi_0_ep>;
                data-lanes = <1 2 3 4>;
                csis-hs-settle = <13>;
                csis-clk-settle = <2>;
                csis-wclk;
                };
       };

};
2

Hi, I’m the Toradex AI Assistant.

I might make mistakes or occasionally get you wrong. Our support team will step in if needed.

(1): Colibri iMX6ULL 扩展音频解码器 MAX98357A

(2): Clocks in imx6ull and imx7d

(3): Verdin iMX8M Plus: MCLK Not Generated on MIPI-CSI Interface

(4): iMX8MP: Generating clock at pin 91 CLKO2 pin

MCLK Generation Issue on Verdin iMX8M Plus

Based on your device tree configuration for the OS05B10 camera sensor, I can see you’re trying to generate MCLK on the Verdin iMX8M Plus(3). The issue you’re experiencing is commonly related to pin muxing configuration.

Pin Muxing Configuration

The key issue is that you need to properly configure the pin muxing to route the CCM_CLKO2 signal to the physical pin(3). Your current configuration references &pinctrl_gpio_hog3, but this pinctrl group needs to be modified to output the clock signal instead of configuring the pin as GPIO(3).

Here’s the correct pin muxing configuration you need to add or modify(3):

&pinctrl_gpio_hog3 {
  fsl,pins =
   // CSI_1_MCLK
   <MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x4>; // SODIMM 91
};

(3)

Alternative Implementation

If the above doesn’t work, you can also try this approach that has been successfully used(4):

pinctrl_gpio_hog3: gpiohog3grp {
    fsl,pins = <
        MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13             0x1c4   /* SODIMM 157 */
        MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2      0x116    /* SODIMM 91 */
    >;
};

(4)

Clock Driver Modifications

Additionally, you may need to ensure the clock is properly enabled in the clock driver(4). Some implementations require modifications to enable CLKO2:

//set and enable CLKO2 24MHZ
clk_set_parent(clks[IMX8MP_CLK_IPP_DO_CLKO2], clks[IMX8MP_CLK_24M]);
clk_prepare_enable(clks[IMX8MP_CLK_IPP_DO_CLKO2]);

(4)

Troubleshooting Steps

  1. Verify Pin Muxing: Ensure that GPIO1_IO15 (SODIMM 91) is muxed to CCM_CLKO2 instead of GPIO function(3)
  2. Check Clock Assignment: Your clock assignments look correct with assigned-clocks, assigned-clock-parents, and assigned-clock-rates(3)
  3. Verify Clock Enable: Use oscilloscope or multimeter to verify that 24MHz clock is actually present on SODIMM 91(3)
  4. Review Device Tree Compilation: Ensure your device tree changes are properly compiled and loaded(3)

The main issue is typically that the pin remains configured as GPIO instead of being muxed to the clock output function(3).

Best regards, Toradex AI Assistant.

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3

Hi @elgin!

I saw you opened another thread.

Were you able to resolve this issue?

Best regards.

4

Yes I solved this issue

5

Hi @elgin!

Could you please share what you did to solve the issue?

Best regards.