iMX8MP: Generating clock at pin 91 CLKO2 pin

Hi,

We want to generate 100Mhz CLK output from the SoM to an external FPGA.
For that we have planned to use pin 91 (CLKO2) of iMX8M-Plus SoM and I configured DTS file as below:

    pinctrl_additionalgpio: additionalgpios {
        fsl,pins = <
            ..
            // according to 8.2.4.299 SW_PAD_CTL_PAD_CLKOUT2 SW PAD Control Register
            MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2          0x16               /* SODIMM 91    - CLKOUT2 */
        >;

But I see just zero on the pin. Do you know what shall we do to get clock out at 100 Mhz from this pin?

Thank you.

Hi @Fide !

Sorry for the delay.

But I have been trying to make the GPIO1_IO15-CLKO2 (and actually GPIO1_IO14-CLKO1 as well for testing purposes) output clock. But without success until now.

I am basing myself on this question from NXP forum: Solved: Re: enable CLKO2 for 24MHz output clock on iMX8MN - NXP Community

Be aware that this question targets IMX8MN and not IMX8MP.

Here are the modifications that I did until now. I set 24MHz as a parent for both pins just for testing.

With this, CLKO2 stays always high, and CLKO1 outputs a clock that seems unstable to me.

Explanation about PAD_CTL used:

0x110 - 0b100010000
DSE_X1 (tried with DSE_X6 also)
FSEL_1_ FAST_SLEW_RATE
ODE_0_ OPEN_DRAIN_DISABLE (tried with enabled as well)
PUE_0_WEAK_ PULL_DOWN
HYS_0_ CMOS
PE_1_ PULL_ENABLE

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
index e44bfb5efe9d..0b49af65b345 100755
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
@@ -216,7 +216,7 @@

 &usb_dwc3_1 {
        disable-over-current;
-       status = "okay";
+       status = "disabled";
 };

 /* Verdin SD_1 */
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi
index e7b3fe432de5..9bbb38698978 100755
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi
@@ -56,7 +56,8 @@
                    <&pinctrl_gpio3>, <&pinctrl_gpio4>,
                    <&pinctrl_gpio7>, <&pinctrl_gpio8>,
                    <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>,
-                   <&pinctrl_hdmi_hog>;
+                   <&pinctrl_hdmi_hog>,
+            <&pinctrl_usb2_en>;
 };

 /* On-module Bluetooth */
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
index be5b89a89157..bd8525cb5d79 100755
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
@@ -1095,8 +1095,7 @@
        pinctrl_gpio_hog3: gpiohog3grp {
                fsl,pins = <
                        MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13             0x1c4   /* SODIMM 157 */
-                       /* CSI_1_MCLK */
-                       MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15             0x1c4   /* SODIMM 91 */
+            MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2      0x116    /* SODIMM 91 */
                >;
        };

@@ -1309,7 +1308,7 @@

        pinctrl_usb2_en: usb2engrp {
                fsl,pins = <
-                       MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR               0x184   /* SODIMM 185 */
+                       MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1              0x116       /* SODIMM 185 */
                >;
        };

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a92cf772720a..7abb48651ebb 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -864,6 +864,14 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
        clk_prepare_enable(clks[IMX8MP_CLK_QOS_ENET_ROOT]);
        clk_prepare_enable(clks[IMX8MP_CLK_ENET_QOS_ROOT]);

+       //set and enable clko1 24mhz
+       clk_set_parent(clks[IMX8MP_CLK_IPP_DO_CLKO1], clks[IMX8MP_CLK_24M]);
+       clk_prepare_enable(clks[IMX8MP_CLK_IPP_DO_CLKO1]);
+
+    //set and enable CLKO2 24MHZ
+    clk_set_parent(clks[IMX8MP_CLK_IPP_DO_CLKO2], clks[IMX8MP_CLK_24M]);
+    clk_prepare_enable(clks[IMX8MP_CLK_IPP_DO_CLKO2]);
+
        imx_register_uart_clocks();

        pr_info("i.MX8MP clock driver probe done\n");

Best regards,

Please find below an example of how to use such a clock upstream for a OV5640 camera. Note that clocks should usually not be pulled neither up nor down as they are push/pull driven. And, yeah, they are open-drain neither. I hope that helps.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9f046930657e9e231a2f9139cdcb611805b19d7c