imx6ULL custom device tree

I have been building a custom embedded Linux build using the Yocto project and Toradex documentation.

I need to use 2 additional UARTS.
The first 3 uarts 1,2,5 are already configured by default.
I want to use uarts 6 and 8.

I have looked a various Toradex documents but i’m struggling to get the 2 uarts enabled.

gives some details of creating a custom.dts file. I can run make dtbs and the file is compiled but the resultant image does not enable uart 6 or 8.

modifying the imx6ull-colibri-eval-v3.dtsi directly (which i was under the impression was not recommended), resulted in more progress.
adding just
&uart6 {
status = “okay”;

enables uart5 ( /dev/ttymxc5 is available)

I could continue to edit this file, but would prefer to use the recommended route of a separate custom file.

How do i achieve this?

Device Tree overlays are recommended for making minor adjustments to the Device tree.

This just leads me back to the same point i am now.

Digging though various book i have used the following steps.

  1. run >bitbake virtual/kernel -c devshell

This give me a new command prompt for running make dtbs

  1. modify the dtsi files to add settings for uart6 & 8
  2. run >make dtbs then >exit
  3. run >bitbake virtual/kernel -f -c compile
  4. run >bitbake my-image

I have currently had to modify the imx6ull-colibri.dtsi and the imx6ull-colibri-eval-v3.dtsi.
This does work.

What i cant seem to do is create a separate custom.dts file and use it.
I have added the file to the Makefile and run the make dtbs and it does generate the custom.dtb file.
But this method fails.

Looking at the generated Tezi+build image, it does not contain the custom.dtb file
Do i need to manually add the custom.dtb file to the Tezi+build image ?
or should this be added by bitbake during the build?

Please follow thid instructions - Build Device Tree Overlays from Source Code article to compile your device tree overlay.

The article says:

This article describes how to build Device Tree overlays without using a higher-level build system such as the Yocto Project/OpenEmbedded

But i am using Yocto… So how do i add a custom device tree within Yocto ?

The device Tree customization article shows the start of the process to add a custom.dts file, but this is incomplete and does not work.

Hi @ObiTwo ,

have a look at this one here.

If you scroll down a bit you will see how you can add your custom device tree there.

In case you have questions please add them here.

Best Regards

Hello @ObiTwo ,
Were you able to have a look at the documentation provided by @kevin.tx ?

Best regards,

Hi Josep,

Yes, I have looked at the documentation, and lots more books too.

A this stage I have modified the existing .dtsi files for my yocto project.

Which has worked.

I was only looking to add 2 additional COM ports and mange to achieve this.

I’m still on a steep learning curve for embedded Linux and Yocto, but getting there.

I do intend to use the patching methods, but as with all things Linux, nothing is ever that easy :blush:

Best regards,









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Hi @ObiTwo ,

Thanks for the update! Glad to hear that you are making progress.

Let us know if we can help you with anything.

Best Regards


I am in the same boat (trying to enable two more UARTs out of Colibri imx6ull). Can you list major steps to achieve that? I am neck-deep into dtsi’s without any grasps of what happens and why.

Here’s what i did to get 2 extra ports working.
This is not the recommended way, but the documentation for this just blows my head.

Get your base bitbake build done. use either the tdx-reference-minimal-image or multimedia image.

From the build directory run >bitbake virtual/kernel -c devshell . this will bring up a new terminal.
leave it running.

You then need to find the imx6ull-colibri.dtsi
this is located in the build/tmp/work-shared/colibri-imx6ull/kenel-source/arch/arm/boot/dts folder.
find the &uart5 entry and add:

&uart6 {
pinctrl-names = “default”;
pinctrl-0 = <&pinctrl_uart6>;

&uart8 {
pinctrl-names = “default”;
pinctrl-0 = <&pinctrl_uart8>;

I also changed the following from the pinctrl_uart1 section. I didn’t need any control lines for any uarts so removed them (commented out) and added the required lines for the uart6 and uart8.

	pinctrl_uart1: uart1-grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX	0x1b0b1	/* SODIMM 33 */
			MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX	0x1b0b1	/* SODIMM 35 */
			//MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS	0x1b0b1	/* SODIMM 27 */
			//MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS	0x1b0b1	/* SODIMM 25 */

	//pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
	//	fsl,pins = <
	//		MX6UL_PAD_JTAG_TDI__GPIO1_IO13		0x70a0 /* SODIMM 31 */
	//		MX6UL_PAD_LCD_DATA18__GPIO3_IO23	0x10b0 /* SODIMM 29 */
	//		MX6UL_PAD_JTAG_TDO__GPIO1_IO12		0x90b1 /* SODIMM 23 */
	//		MX6UL_PAD_LCD_DATA19__GPIO3_IO24        0x10b0 /* SODIMM 37 */
	//	>;

	pinctrl_uart2: uart2-grp {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX	0x1b0b1 /* SODIMM 36 */
			MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX	0x1b0b1 /* SODIMM 38 */
			//MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS	0x1b0b1 /* SODIMM 32 */
			//MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS	0x1b0b1 /* SODIMM 34 */
	pinctrl_uart5: uart5-grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX	0x1b0b1 /* SODIMM 19 */
			MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX	0x1b0b1 /* SODIMM 21 */
	pinctrl_uart6: uart6-grp {
		fsl,pins = <
			MX6UL_PAD_CSI_MCLK__UART6_DTE_RX	0x1b0b1 /* SODIMM 75 */
	pinctrl_uart8: uart8-grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA20__UART8_DTE_RX	0x1b0b1	/* SODIMM 88 */
			MX6UL_PAD_LCD_DATA21__UART8_DTE_TX	0x1b0b1	/* SODIMM 86 */

Next find the imx6ull-colibri-eval-v3.dtsi
find the &ecspi1 section and disable it! This is because it uses the same line as one of the additional uarts. I modded as below:

&ecspi1 {
status = “disabled”;

mcp2515: can@0 {
	compatible = "microchip,mcp2515";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can_int>;
	reg = <0>;
	clocks = <&clk16m>;
	interrupt-parent = <&gpio2>;
	interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
	spi-max-frequency = <10000000>;
	vdd-supply = <&reg_3v3>;
	xceiver-supply = <&reg_5v0>;
	status = "disabled";

/* To keep the CAN controller enabled by default,
 * disable conflicting spidev.
spidev0: spidev@0 {
	status = "disabled";


Finally enable the 2 uarts below the &uart5 section

&uart6 {
status = “okay”;

&uart8 {
status = “okay”;

Save those 2 files.
From the terminal opened by the devshell command run:

make dtbs

then you can exit the terminal.
then run

bitbake virtual/kernel -f -c compile

then rebuild your image

bitbake your-image.

This worked for me. Hope it helps.

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Hi @ObiTwo ,

Thanks a lot for this detailed description :tada:

@Logosol if you have more questions feel free to post them here. If the questions are different then you can open a new question and we would be happy to help you there.

Best Regards

James, Thank you so much for detailed instructions! I’d buy you a coffee/beer/wine in the real life if I had a chance :wink:

I did not have time yesterday to implement them, today first try resulted with only uart8 available, most probably there’s a typing error in my implementation somewhere.

@kevin.tx: As @ObiTwo mentioned, Device Trees are very convoluted way to achieve common-day tasks in developer’ life. The example Pin Multiplexing - Changing Pin Functionalities in the Linux Device Tree | Toradex Developer Center, just scratches the area. A more detailed example, with hierarchy of dts/dtsi files, and explanation why and where some obscure parameter will be much appreciated.

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Hi @Logosol ,

Thank you for the feedback.

I will forward that to the documentation team.

Best Regards

In addition to @ObiTwo’ changes, I had to make couple more to enable uart6:
In “pinctrl_gpio2: gpio2-grp { /* Camera */” group:

  • disable MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */
  • disable MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */
		pinctrl_gpio2: gpio2-grp { /* Camera */
			fsl,pins = <
				MX6UL_PAD_CSI_DATA04__GPIO4_IO25	0x10b0 /* SODIMM 69 */
/*				MX6UL_PAD_CSI_MCLK__GPIO4_IO17		0x10b0 /* SODIMM 75 */
				MX6UL_PAD_CSI_DATA06__GPIO4_IO27	0x10b0 /* SODIMM 85 */
/*				MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18	0x10b0 /* SODIMM 96 */
				MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x10b0 /* SODIMM 98 */

Now, time to tackle the next UART task: Enabling 250kbps (easier) / 1250kbps (harder). Using 5MHz closk, 250kbps is doable, but for 1250kbps, another clock should be found and switched to.

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