Verdin IMX8MP and KSZ8873

Technical Support
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10

Hi @andi.tx,

This is our U-Boot device tree:

&fec {
	fsl,magic-packet;
	phy-handle = <&ethphy1>;
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	status = "okay";

	/* configure 50MHz REF and PHY_REF clock */
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
					<&clk IMX8MP_SYS_PLL2_100M>,
					<&clk IMX8MP_SYS_PLL2_50M>;
	assigned-clock-rates = <0>, <100000000>, <50000000>, <0>;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		status = "okay";

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			micrel,led-mode = <0>;
			reg = <1>;

			interrupt-parent = <&gpio3>;
			interrupts = <IRQ_TYPE_LEVEL_LOW>;

			reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
			reset-assert-us = <1000>; /* see datasheet TABLE 5-8 */
			reset-deassert-us = <10>; /* see datasheet TABLE 5-8 */

			status = "okay";


		};
	};
};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3 /* ETH_AUX_MDC */
			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3 /* ETH_AUX_MDIO */
			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x40000086 /* ETH_AUX_REFCLK */
			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91 /* ETH_AUX_RXD0 */
			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91 /* ETH_AUX_RXD1 */
			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f /* ETH_AUX_TXD0 */
			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f /* ETH_AUX_TXD1 */
			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x00000090 /* ETH_AUX_RXER */
			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f /* ETH_AUX_TXEN */
			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x1f /* ETH_AUX_CRS_DV */
			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x00000046 /* !ETH_AUX_INT */
			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x00000006 /* !ETH_AUX_PHY_RESET */
		>;
	};

In board/toradex/verdin-imx8mp/verdin-imx8mp.c we have configured GPR1 to 50MHZ output clock:

static int setup_fec(void)
{
	struct iomuxc_gpr_base_regs *gpr =
		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;

	// power down to 1
	gpio_request(FEC_EN, "FEC_EN");
	gpio_direction_output(FEC_EN, 1);


	/* Enable RGMII TX clk output */
	setbits_le32(&gpr->gpr[1], BIT(22));
	setbits_le32(&gpr->gpr[1], IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
	printf("SETUP FEC BIT22 -> 1\n");
	return 0;
}

MDIO seems to be woking perfectly in U-Boot.

Net:   eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
Verdin iMX8MP # mdio list
FEC1:
1 - Generic PHY <--> ethernet@30be0000
ethernet@30bf0000:

In linux kernel messages is nothing about FEC or second ethernet instead of this:

[    1.328458] reg-fixed-voltage regulator-module-eth1phy: Failed to register regulator: -517

I tried steps and DTS from similar post Enabling second ethernet connection to a fully hardware configured switch IC
with no success.