Verdin iMX8M Plus: MCLK Not Generated on MIPI-CSI Interface

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Hello,

Thank you for reaching out with your question about the MCLK signal on the MIPI-CSI interface of the Verdin iMX8M Plus. Let’s go through some steps to help you troubleshoot and resolve this issue:

  1. Device Tree Configuration: Double-check that the camera node in your device tree is correctly configured. The MCLK (Master Clock) signal is typically controlled by a specific clock node. Ensure that the clock source for the MIPI-CSI interface is properly defined and enabled in your DTS file.

  2. Clock Source: Verify that the clock source for the MCLK is set up correctly. This may involve specifying the correct clock parent and frequency in the device tree. Look for entries related to clocks, clock-names, and assigned-clocks in your camera node or related nodes.

  3. Kernel Configuration: Make sure your kernel configuration supports the MIPI-CSI interface and the specific camera you are using. This might require enabling certain drivers or modules in the kernel configuration.

  4. Check for Errors: Use the dmesg command to look for any error messages related to the MIPI-CSI interface or the camera. This can provide clues if there are issues with the clock or other related components.

  5. Documentation and Examples: Review any available documentation or example configurations for the Verdin iMX8M Plus. These resources can offer insights into the correct setup and configuration for the MIPI-CSI interface.

I hope these steps help you resolve the issue. If you have any further questions, feel free to ask.

Best regards,
Toradex AI Assistant

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Why is USB_2_OC# a GPIO on Verdin IMX8MP.