Hello everyone,
I am trying to make the PCI express work (to install a NVME drive) and I have this error message at boot. I use the latest BSP 5. I did not modify the device tree except adding RPMSG and disabling a SPI port.
# dmesg | grep pci
[ 0.135499] imx8-pcie-phy 32f00000.pcie-phy: failed to get imx pcie phy clock
[ 1.298357] ehci-pci: EHCI PCI platform driver
[ 1.938115] imx6q-pcie 33800000.pcie: PLL REF_CLK is used!.
[ 1.950769] imx6q-pcie 33800000.pcie: PCIe PHY PLL clock is locked.
[ 2.097343] imx6q-pcie 33800000.pcie: PCIe PLL locked after 0 us.
[ 2.106057] imx6q-pcie 33800000.pcie: host bridge /pcie@33800000 ranges:
[ 2.121542] imx6q-pcie 33800000.pcie: IO 0x1ff80000..0x1ff8ffff -> 0x00000000
[ 2.134024] imx6q-pcie 33800000.pcie: MEM 0x18000000..0x1fefffff -> 0x18000000
[ 3.135492] imx6q-pcie 33800000.pcie: Phy link never came up
[ 3.141202] imx6q-pcie 33800000.pcie: failed to initialize host
[ 3.147222] imx6q-pcie 33800000.pcie: unable to add pcie port.
It seems weird that the imx6 driver is loading since I am using a imx8. Do you have any clue ?
Many thanks to everyone
Hello @luciolis ,
One of our customers had a similar issue and modifying the following node seemed to fix the issue for them
@pcie0 {
ext_osc = <0>;
};
Could you maybe give it a try?
Best Regards,
Janani
Hello @saijanani.tx,
Thanks for the tip. I added the following snippet to my overlay:
fragment@1 {
target = <&pcie0>;
__overlay__ {
ext_osc = <0>;
};
};
And there is no change. Do you think it is because the change is in an overlay and not in the source code?
Can you enable PCI-e on your end?
Best regards,
Adrian
Hello @luciolis ,
As verdin iMX8M plus is still a development product, we have not yet tested all these features. But we have a handful of customers who have told us that they could already get their PCIe working/ basic tests were successful.
So, we are trying to reach out to them to check if they have any tweaks etc., that made it work. This might, however, take some while. But we will make sure to keep you updated.
Thanks for your understanding.
Best Regards,
Janani
Hello @luciolis ,
As promised, we reached out to our customers asking what did they do to successfully get the PCIe working for their application and here is the answer:
We have tested the iMX8M-Plus’s PCIe bus with 2 peripherals:
- Advantech SQF-CMSV4-1T-E8E, miniPCIe PCIe 1TB SSD: https://www.advantech.com/products/1b857a1c-42d5-4aaa-a275-1b27f6c66aec/sqf-cms-710/mod_4f16ee40-e559-49c2-9585-5f0ced227d66
This is an SSD, we plugged It to Dahlia board and checked read/write speed. Physical layer connected at PCIe Gen3 speed. We didn’t need any driver, the device recognized by Linux (Toradex reference image) automatically.
- Second peripheral that we test it with was Arria 10 GX FPGA Development board’s PCIe bus. We connect FPGA PCIe bus to Dahlia Board’s Mini PCIe connector via a passive adaptor (like TX → RX and vice versa). FPGA was configured as a memory device on the PCIe bus. At the boot time, Dahlia board enumerates FPGA over the PCIe and established the connection at Gen3 speed. Again we didn’t need any special driver. To access to the FPGA as a memory, we simply uses open() and mmap() API of Linux in our application code like below:
int fd = open(/sys/devices/platform/soc@0/33800000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0//resource2, O_RDWR | O_SYNC);
void* ptr = mmap(0, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
They use the same Hardware as you and was able to test it successfully. Was this helpful to you? Do you think you could try these suggestions out?
Best Regards,
Janani
Hello @saijanani.tx ,
Thanks for the fast answer. Do you know if, even if nothing is connected to the mini pcie port, there is a /sys/devices/platform/soc@0/33800000.pcie node? With no peripheral at all, I have the same errors and the message “unable to add pcie port”.
I would add that i have the 2GB 0061 Plus Quad board V 1.0B
hello @luciolis ,
Thank you for your patience on this regard. But, now I have the update.
So, the other customers also had the error when there were no PCIE devices connected, but they confirmed that this hadn’t affected their application.
our customer was also kind enough to share some outputs when there was no PCIE card plugged in:
root@verdin:~# dmesg | grep pci
[ 0.154039] imx8-pcie-phy 32f00000.pcie-phy: failed to get imx pcie phy clock
[ 1.284290] ehci-pci: EHCI PCI platform driver
[ 1.915388] imx6q-pcie 33800000.pcie: PLL REF_CLK is used!.
[ 1.928035] imx6q-pcie 33800000.pcie: PCIe PHY PLL clock is locked.
[ 2.073755] imx6q-pcie 33800000.pcie: PCIe PLL locked after 0 us.
[ 2.080087] imx6q-pcie 33800000.pcie: host bridge /pcie@33800000 ranges:
[ 2.090707] imx6q-pcie 33800000.pcie: IO 0x1ff80000..0x1ff8ffff -> 0x00000000
[ 2.106919] imx6q-pcie 33800000.pcie: MEM 0x18000000..0x1fefffff -> 0x18000000
[ 3.111207] imx6q-pcie 33800000.pcie: Phy link never came up
[ 3.116913] imx6q-pcie 33800000.pcie: failed to initialize host
[ 3.122865] imx6q-pcie 33800000.pcie: unable to add pcie port.
Here is the content of the /sys/devices/platform/soc@0/ folder when there is no PCIe card plugged:
root@verdin:/sys/devices/platform/soc@0# ls -l
total 0
drwxr-xr-x 3 root root 0 Sep 20 10:43 100000.caam-sm
drwxr-xr-x 19 root root 0 Sep 20 10:43 30000000.bus
drwxr-xr-x 6 root root 0 Sep 20 10:43 30400000.bus
drwxr-xr-x 22 root root 0 Sep 20 10:43 30800000.bus
drwxr-xr-x 7 root root 0 Sep 20 10:43 30c00000.bus
drwxr-xr-x 17 root root 0 Sep 20 10:43 32c00000.bus
-r--r--r-- 1 root root 4096 Sep 20 14:18 consumers
-rw-r--r-- 1 root root 4096 Sep 20 14:18 driver_override
-r--r--r-- 1 root root 4096 Sep 20 14:09 modalias
lrwxrwxrwx 1 root root 0 Sep 20 14:18 of_node -> ../../../firmware/devicetree/base/soc@0
drwxr-xr-x 2 root root 0 Sep 20 14:18 power
lrwxrwxrwx 1 root root 0 Sep 20 10:43 subsystem -> ../../../bus/platform
-r--r--r-- 1 root root 4096 Sep 20 14:18 suppliers
-rw-r--r-- 1 root root 4096 Sep 20 10:43 uevent
But when the PCIe Mini SSD is plugged into the Dahlia Board’s mini PCIe bus, it all worked fine again. you could even lspci -v and check that the PCIe works at gen3 max speed.
I hope this helps.
Thanks and Best regards,
Janani
