I’m using a 3rd party LVDS display that uses dual LVDS channels. I’d like to make it work on my verdin-imx8mp SoM with my verdin dev board. I have a custom adapter board that connects to the DSI output, made per Toradex’s reference dsi-to-lvds adapter schematic. I’m currently using Toradex’s latest 7.0.0 yocto BSP. I have tried both the cutting edge 6.6 kernel, and the slightly older 7.0.0 BSP with the 5.15 kernel.
When I comment out the 2nd channel (remove lvds_out_panelB/panel_in_lvdsB endpoint links), the display does show an image. It’s not the correct image because I’m only sending data to one of it’s two LVDS inputs. But as soon as I enable the 2nd channel, the display just shows a blank, black screen. By a happy accident, I accidentally powered on the board once with a device tree that was intended for a different display and I did get an image on the screen. After some trial & error, I determined that the clock-frequency setting of 146MHz is the issue.
The display shows an image when set to 146MHZ in single lvds mode. But not in dual mode. The other device tree I accidentally applied once uses 95.97MHz. That frequency (with no other changes to the below device tree) does show an image. After more trial and error, I learned that I can see an image if the clock-frequency is set anywhere between 95.57 MHz to 99.20MHz. If I go just 0.05MHz more outside that band, I get a black screen.
Below is my latest device tree, including the 146MHz frequency that the panel expects. These settings show the black screen, but do show an image if I change only clock-frequency to <95970000 95970000 95970000>;. But of course the image is choppy due to the wrong frequency.
How can I get the sn65dsi84 chip to output 146MHz (or rather 146/2 MHz on each channel)?
Hi, I’m the Toradex AI Assistant. The Toradex Support team will follow up with you shortly!
Did you like my answer?
Based on the context provided, it seems like you are experiencing issues with setting the correct clock frequency for a dual LVDS display using the SN65DSI84 chip on a Verdin iMX8MP SoM. The problem arises when trying to achieve the desired 146MHz frequency in dual LVDS mode, which results in a black screen, while a lower frequency range (95.57 MHz to 99.20 MHz) works but is not optimal.
Here are a few suggestions to troubleshoot and potentially resolve the issue:
Check SN65DSI84 Configuration: Ensure that the SN65DSI84 chip is correctly configured for dual LVDS mode. This includes verifying the register settings for the chip, as incorrect settings could prevent the chip from outputting the desired frequency.
Device Tree Configuration: Double-check the device tree configuration to ensure that all necessary properties for dual LVDS mode are correctly set. This includes ensuring that the dual-lvds-odd-pixels and dual-lvds-even-pixels properties are correctly defined and that the endpoints are properly linked.
Clock Source and PLL Settings: Investigate the clock source and PLL settings for the SN65DSI84. The issue might be related to how the clock is being generated or divided. Ensure that the PLL is correctly configured to output the desired frequency.
Signal Integrity: Consider the possibility of signal integrity issues on the custom adapter board. Ensure that the traces are properly designed for high-frequency signals and that there is adequate termination to prevent reflections.
Consult SN65DSI84 Datasheet: Review the SN65DSI84 datasheet for any specific requirements or limitations regarding dual LVDS operation and clock frequencies.
Kernel and Driver Support: Ensure that the kernel and driver versions you are using fully support the SN65DSI84 and the dual LVDS configuration. There might be patches or updates available that address similar issues.
If these suggestions do not resolve the issue, it may be beneficial to reach out to Toradex technical support for further assistance, as they can provide more specific guidance based on your hardware setup and configuration.
Please, also check if these links can help you solve your problem:
Also, I did some more testing on my end by adding printk statements to the sn64dsi84 driver to dump all the i2c register configs that it’s using. Interestingly, when I increment the clock-frequency in my device tree from 99.20MHz (which shows an image) and 99.25MHz(which has a blank screen), none of the i2c registers change (it doesn’t switch to a different CHA_DSI_CLK_RANGE value or anything like that. The one bit that changes is that the CHA_SYNCH_ERR is set by the sn65dsi84 chip. From the datasheet: CHA_SYNCH_ERR
When the DSI channel A packet processor detects an HS or VS*
synchronization error, that is, an unexpected sync packet; this bit is set; this*
bit is cleared by writing a ‘1’ value.*
So it seems some other piece of kernel code is setting the DSI clock that feeds in to the sn65dsi84 chip. And it seems like that clock frequency is the cause of the issue, moreso than the sn65dsi84 chip.
Can you help me find the kernel code that reads the “clock-frequency” field of my device tree and plumbs that into the clock used on the Verdin’s DSI output? I feel like our issue lies somewhere in there.
Debugging the kernel behavior is usually complex and time-consuming, not to mention that it involves a very good level of knowledge about the kernel itself.
As you’re using a 3rd party LVDS display, we are not sure that there is an issue with the kernel, so if you have interest, we can recommend partners that have experience in evaluating what could be the issue with the display you are using or providing training to accelerate projects.
Please, let me know if you would like such a recommendation.
Lucas, I understand the 3rd party display complicates things. Can you recommend a different lvds display supported by Toradex that uses the dual lvds architecture? I have a 10" Toradex display but a believe that only supports single currently lvds, right?
Riverdi is a Toradex partner that has various models and types of displays. Please, feel free to contact them. They will help you find a good solution for your issue.
