Native LVDS interface on Verdin AM62

Hi,
I have been trying to enable the lvds interface on our verdin module so we can use it on a custom board. I am using a custom Yocto B2QT image. I created an overlay that I apply at boot time, however there is no picture on our display.

&main_pmx0 {
    
    pinctrl_oldi: main-oldi0-pins-default {
        pinctrl-single,pins = <
			AM62X_IOPAD(0x0260, PIN_OUTPUT, 0) /* (AA5) OLDI0_A0N */
			AM62X_IOPAD(0x025c, PIN_OUTPUT, 0) /* (Y6) OLDI0_A0P */
			AM62X_IOPAD(0x0268, PIN_OUTPUT, 0) /* (AD3) OLDI0_A1N */
			AM62X_IOPAD(0x0264, PIN_OUTPUT, 0) /* (AB4) OLDI0_A1P */
			AM62X_IOPAD(0x0270, PIN_OUTPUT, 0) /* (Y8) OLDI0_A2N */
			AM62X_IOPAD(0x026c, PIN_OUTPUT, 0) /* (AA8) OLDI0_A2P */
			AM62X_IOPAD(0x0278, PIN_OUTPUT, 0) /* (AB6) OLDI0_A3N */
			AM62X_IOPAD(0x0274, PIN_OUTPUT, 0) /* (AA7) OLDI0_A3P */
			AM62X_IOPAD(0x0280, PIN_OUTPUT, 0) /* (AC6) OLDI0_A4N */
			AM62X_IOPAD(0x027c, PIN_OUTPUT, 0) /* (AC5) OLDI0_A4P */
			AM62X_IOPAD(0x0288, PIN_OUTPUT, 0) /* (AE5) OLDI0_A5N */
			AM62X_IOPAD(0x0284, PIN_OUTPUT, 0) /* (AD6) OLDI0_A5P */
			AM62X_IOPAD(0x0290, PIN_OUTPUT, 0) /* (AE6) OLDI0_A6N */
			AM62X_IOPAD(0x028c, PIN_OUTPUT, 0) /* (AD7) OLDI0_A6P */
			AM62X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AD8) OLDI0_A7N */
			AM62X_IOPAD(0x0294, PIN_OUTPUT, 0) /* (AE7) OLDI0_A7P */
			AM62X_IOPAD(0x02a0, PIN_OUTPUT, 0) /* (AD4) OLDI0_CLK0N */
			AM62X_IOPAD(0x029c, PIN_OUTPUT, 0) /* (AE3) OLDI0_CLK0P */
			AM62X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (AE4) OLDI0_CLK1N */
			AM62X_IOPAD(0x02a4, PIN_OUTPUT, 0) /* (AD5) OLDI0_CLK1P */
        >;
    };
};

This is how I try to enable the pins, then I configure the dss ports and dss likewise:

&dss {
    status = "okay";
    pinctrl-0 = <&pinctrl_oldi>;
};

&dss_ports {
	#address-cells = <1>;
	#size-cells = <0>;
	/* VP1: LVDS Output (OLDI TX 0) */
	port@0 {
		reg = <0>;
		oldi_out0: endpoint {
			remote-endpoint = <&lvds_in0>;
		};
	};

	/* VP1: LVDS Output (OLDI TX 1) */
	port@2 {
		reg = <2>;
		oldi_out1: endpoint {
			remote-endpoint = <&lvds_in1>;
		};
	};
    
};

Also the panel timings

    backlight_custom: backlight-custom {
        compatible = "pwm-backlight";
        brightness-levels = <0x00 0x2d 0x3f 0x58 0x77 0x9e 0xcb 0xff>;
        default-brightness-level = <0x04>;
    };

        custom_panel: panel-lvds-custom {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				compatible = "panel-lvds";
                backlight = <&backlight_custom>;
				data-mapping = "vesa-24";
				height-mm = <0x35>;
				width-mm = <0x46>;

				panel-timing {
					clock-frequency = <0x30d4000>;
					hactive = <0x140>;
					vactive = <0xf0>;
					hback-porch = <0x27>;
					vfront-porch = <0x08>;
					hfront-porch = <0x08>;
					vback-porch = <0x08>;
					vsync-len = <0x04>;
					hsync-len = <0x04>;
					de-active = <0x00>;
					hsync-active = <0x01>;					
					vsync-active = <0x00>;				
					pixelclk-active = <0x00>;

				};

        port@0 {
            reg = <0x00>;
            
            lvds_in0: endpoint {
                remote-endpoint = <&oldi_out0>;
            };
        };

        port@1 {
            reg = <0x01>;
            
            lvds_in1: endpoint {
                remote-endpoint = <&oldi_out1>;
            };
        };
    };

I have based a lot of the overlay on the mezzanine_panel-lvds-dual-channel overlay. We have measured the OLDI signals and all the data signals are there, however the CLK signals are not. Is there something that needs to be enabled for the OLDI_CLK0 and OLDI_CLK1? I have tried disabling other things in my overlay, like the dsi_bridge, but the result was the same. I have tried different panel timings, and different panels from the panel-simple.c file as suggested on some TI forums, which also produced no results. I have also added some debugging tools like kmstest to my image so I can test if the timings are applied, which confirmed the correct timings of the panel. I can also see in the dmesg logs that the panel has been added successfuly.

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It looks like you’ve done a thorough job setting up your device tree overlay for enabling the LVDS interface on the Verdin AM62. However, there are a few things you might want to check or try to ensure that the OLDI_CLK signals are properly enabled:

  1. Check the Clock Configuration:
    Ensure that the clock source for the OLDI (LVDS) interface is properly configured. Sometimes, the clock might need to be explicitly enabled or configured in the device tree.

  2. Verify Pin Multiplexing:
    Double-check the pin multiplexing settings to ensure that the pins are correctly configured for the OLDI_CLK signals. You might need to refer to the AM62x TRM (Technical Reference Manual) for the correct pin settings.

  3. Check for Additional Clock Nodes:
    There might be additional clock nodes that need to be enabled or configured in the device tree. Look for any clock-related nodes in the device tree documentation or reference device trees.

  4. Enable the Display Subsystem:
    Ensure that the display subsystem (DSS) is fully enabled and configured. Sometimes, additional properties or nodes might be required to fully enable the DSS.

  5. Debugging with Kernel Logs:
    Use kernel logs to debug the issue further. You can add debug prints in the relevant kernel drivers (e.g., panel-lvds, dss) to see if the clocks are being enabled and configured correctly.

  6. Reference Existing Overlays:
    Compare your overlay with existing overlays that are known to work, such as the mezzanine_panel-lvds-dual-channel overlay you mentioned. Look for any differences that might be causing the issue.

  7. Consult TI Forums and Documentation:
    Since the Verdin AM62 is based on a TI SoC, consulting TI forums and documentation might provide additional insights or solutions to the issue.

Here is a checklist of things to verify in your device tree overlay:

  • Ensure the &dss node is correctly configured and enabled.
  • Verify the pinctrl settings for the OLDI_CLK pins.
  • Check if there are any additional clock nodes that need to be enabled.
  • Ensure the panel timings are correctly specified.
  • Look for any additional properties or nodes required for the DSS.

If you have already tried all these steps and the issue persists, it might be helpful to share the relevant kernel logs and any additional information you have gathered during your debugging process. This can provide more context and help in identifying the root cause of the issue.

Please, also check if these links can help you solve your problem:

AM62 + Dahlia + 10" Display.

Hello @karamanr,

I apologize for the delay on this topic.

We will look into this shortly.

Best Regards,
Bruno

Hi @bruno.tx

Thank you for your reply. Have you had the chance to look into the problem with the clock signal ?

We are in tricky situation as we originally started developing our product with the Colibri-imx6ull and there we had the screen fully working. Now, after a recommendation from Toradex, we have migrated to the Verdin and we only miss the screen integration. We would really appreciate your assistance in this matter.

Thank you very much for your cooperation and I look forward to hearing from you!

Hello @karamanr,

What display are you using?

Your timings are not very sound for most displays, as it has a very low resolution (320x240) and a high enough clock frequency to display at hundreds of frames per second.

Also, if your display is of a low resolution and not dual-channel, the most appropriate starting point for an overlay would be verdin-am62_panel-cap-touch-10inch-lvds_overlay.dts.

Apart from the timings, the device tree you sent is mostly correct, however you can remove the pinctrl_oldi node.
The LVDS pins can only be used for LVDS in the AM62, so no pinmuxing is needed.
With the current configuration, the pins are being given to the SoC’s RGB output, which cannot use them. This is incorrect and may cause the LVDS interface not to work.

Best Regards,
Bruno