MIPI DSI display on i.MX8M Plus (1200x1920@60.0, 167.1 MHz)

Technical Support
4

MIPI DSI Clock Configuration on Verdin iMX8M Plus with Torizon OS 6.8.2

Your issue with the 168 MHz pixel clock appears to be related to a known limitation in the i.MX8M Plus MIPI DSI clock configuration. Based on your Torizon OS 6.8.2 setup, here’s what’s happening and how to address it:

Root Cause Analysis

The i.MX8M Plus has a fixed video PLL configuration that limits available pixel clock frequencies(1). The Verdin iMX8M Plus supports up to 1920x1200p60 display per LCDIF if no more than 2 instances are used simultaneously, with one LCDIF driving MIPI DSI up to UWHD and WUXGA(1).

Your observed behavior where video_pll1_out shows 650000000 Hz instead of your requested 1008000000 Hz suggests the PLL configuration is being overridden by the kernel’s clock framework.

Known Clock Configuration Issues

A community member documented a similar issue with DSI clock configuration(2). The problem stems from the i.MX8M Plus having a fixed root video clock that feeds all video interfaces, and these interfaces can only divide that root clock in specific ways(2).

The issue occurs because the fixed 1039.5MHz couldn’t be divided down accurately enough to make a pixel clock that feeds the 25MHz requirement sufficiently with the clock ranges/timings the bridge driver configures(2).

Recommended Solutions

1. Enable Dynamic PLL Rate Configuration

Since commit b09c68dc57c9 (“clk: imx: pll14xx: Support dynamic rates”), the video PLL can be set arbitrarily. You’ll need to enable CLK_SET_PARENT on the i.MX8MP pixel clocks so they can reconfigure the video PLL to be ideal(2).

However, note that this commit was later reverted because both pixel clocks will fight to reconfigure the root video PLL. For a single display use-case, this approach works well(2).

2. Alternative Overlay Configuration

Try this modified overlay approach for your MIPI DSI configuration:

&mipi_dsi {
    status = "okay";
    #address-cells = <1>;
    #size-cells = <0>;

    panel@0 {
        compatible = "urt,umoh-9866md-t";
        reg = <0>;
        status = "okay";
        
        backlight = <&backlight>;
        reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
        
        port {
            umoh_9866md_t_in: endpoint {
                remote-endpoint = <&dsi_out_panel>;
            };
        };
    };
    
    ports {
        #address-cells = <1>;
        #size-cells = <0>;

        port@1 {
            reg = <1>;
            dsi_out_panel: endpoint {
                remote-endpoint = <&umoh_9866md_t_in>;
                data-lanes = <1 2 3 4>;
            };
        };
    };
};

(3)

3. Clock Verification Commands

To verify your clock configuration:

cat /sys/kernel/debug/clk/clk_summary | grep -C 5 video

(1)

MIPI DSI Interface Specifications

According to the Verdin iMX8M Plus datasheet, the MIPI DSI interface uses the MIPI D-PHY for the physical layer, compatible with version 1.2 specifications, with a maximum data transfer per lane of 1.5Gbps(4). It supports resolutions up to 1920x1080p60 with 24-bit RGB and also supports a 10Mbps data rate for low power operation(4).

Next Steps

  1. Check if your kernel supports the dynamic PLL rate configuration
  2. Verify the exact pixel clock being generated using the debug commands
  3. Consider creating a custom kernel build with the necessary clock patches if the standard configuration doesn’t meet your 168 MHz requirement

The community has documented successful implementations with similar challenges, so this configuration should be achievable with the right approach.

Best regards, Toradex AI Assistant.

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