Hello!
I’m using a UMOH-9866MD-T MIPI DSI panel on a Toradex Verdin i.MX8MP with custom timings (1200×1920 @ ~60 Hz, 168 MHz pixel clock, 4 lanes, RGB888). The display manufacturer’s datasheet specifies PCLK = 168 MHz (HTOTAL 1311, VTOTAL 2124). In the overlay, we override VIDEO_PLL1 to 1008000000 Hz and MEDIA_DISP1_PIX to 168000000 Hz via media_blk_ctrl, assigning clocks/rates/parents. But clk_summary shows:
video_pll1_out = 650000000 Hz
media_disp1_pix / lcdif_pixel_clk = 162500000 Hz (~ 650M / 4)
The DSI PHY reference clock is also stuck at 12 MHz despite attempts to force it to 24/25 MHz. Panel remains blank. DRM probe succeeds, atomic commit runs, but vblank times out quickly.
Without these adjustments, of course, the display remained black. Same as now.
Is there a known limitation or required kernel patch for the exact 168 MHz pixel clock on i.MX8MP MIPI DSI? Any recommended PLL multiplier/divider or DTS pattern to force 168 MHz pixel + 24/25 MHz PHY, or the direction to diagnose this?
Happy to share full overlay, clk_summary, dmesg (with drm.debug=0x1f), and driver code.
Thanks in advance for any guidance!
Driver parameters:
#define UMOH9866MD_HACTIVE 1200
#define UMOH9866MD_HSYNC 10
#define UMOH9866MD_HFP 83
#define UMOH9866MD_HBP 18
#define UMOH9866MD_VACTIVE 1920
#define UMOH9866MD_VSYNC 4
#define UMOH9866MD_VFP 168
#define UMOH9866MD_VBP 32
#define UMOH9866MD_REFRESH_HZ 60
#define UMOH9866MD_HTOTAL \
(UMOH9866MD_HACTIVE + UMOH9866MD_HFP + UMOH9866MD_HSYNC + \
UMOH9866MD_HBP)
#define UMOH9866MD_VTOTAL \
(UMOH9866MD_VACTIVE + UMOH9866MD_VFP + UMOH9866MD_VSYNC + \
UMOH9866MD_VBP)
#define UMOH9866MD_PCLK_HZ \
((unsigned long long)UMOH9866MD_HTOTAL * \
(unsigned long long)UMOH9866MD_VTOTAL * \
(unsigned long long)UMOH9866MD_REFRESH_HZ)
#define UMOH9866MD_PCLK_KHZ (UMOH9866MD_PCLK_HZ / 1000ULL)
#define UMOH9866MD_WIDTH_MM 95
#define UMOH9866MD_HEIGHT_MM 152
#define UMOH9866MD_MODE_FLAGS \
(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_VIDEO_HSE)
static const struct drm_display_mode umoh9866md_default_mode = {
.hdisplay = UMOH9866MD_HACTIVE,
.hsync_start = UMOH9866MD_HACTIVE + UMOH9866MD_HFP,
.hsync_end = UMOH9866MD_HACTIVE + UMOH9866MD_HFP + UMOH9866MD_HSYNC,
.htotal = UMOH9866MD_HACTIVE + UMOH9866MD_HFP + UMOH9866MD_HSYNC +
UMOH9866MD_HBP,
.vdisplay = UMOH9866MD_VACTIVE,
.vsync_start = UMOH9866MD_VACTIVE + UMOH9866MD_VFP,
.vsync_end = UMOH9866MD_VACTIVE + UMOH9866MD_VFP + UMOH9866MD_VSYNC,
.vtotal = UMOH9866MD_VACTIVE + UMOH9866MD_VFP + UMOH9866MD_VSYNC +
UMOH9866MD_VBP,
.clock = (int)UMOH9866MD_PCLK_KHZ, /* kHz */
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
.width_mm = UMOH9866MD_WIDTH_MM,
.height_mm = UMOH9866MD_HEIGHT_MM,
};
Overlay segment:
// i.MX 8 MIPI DSI
&mipi_dsi {
status = "okay";
panel@0 {
status = "okay";
compatible = "urt,umoh-9866md-t";
reg = <0>;
backlight = <&backlight>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
port {
umoh_9866md_t_in: endpoint {
remote-endpoint = <&umoh_9866md_t_out>;
};
};
};
port@1 {
reg = <1>;
umoh_9866md_t_out: endpoint {
remote-endpoint = <&umoh_9866md_t_in>;
data-lanes = <4>;
};
};
};
&media_blk_ctrl {
status = "okay";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
<&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
<&clk IMX8MP_CLK_MEDIA_ISP>,
<&clk IMX8MP_VIDEO_PLL1>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-rates = <500000000>,
<200000000>,
<168000000>,
<0>,
<500000000>,
<1008000000>,
<25000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_VIDEO_PLL1_OUT>,
<&clk IMX8MP_VIDEO_PLL1_OUT>,
<&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_CLK_24M>,
<&clk IMX8MP_CLK_24M>;
};
&lcdif1 {
status = "okay";
};
