Memory layout on an iMX8M Mini

[hfranco.tx]

Hi @ksalamun,

Let me go through your questions. Let me know if something isn’t clear.

@ksalamun

On the wiki page, it is 0xB_FFFF_FFFF, while in the reference manual, the end address of the DDR range is 0x2_3FFF_FFFF. Moreover, DDR range from 0x1_0000_0000 to 0xB_FFFF_FFFF would mean that the total size of DDR is ~43 GB, which doesn’t make much sense.

There was indeed a typo in our article. I already submitted it to our team so they can correct it. The full address for Verdin is 0x1_0000_0000 to 0x2_3FFF_FFFF for cortex A53 and 0x4000_0000 to 0xFFFF_FFFF, which is accessible by A54 and M4.
0xFFFF_FFFF would mean approximately 4GB of addressable memory. Which makes sense now. Not this is only the addressable memory, not the real physical memory that is being used by the system.

@ksalamun

Secondly, according to the reference manual, the DDR consists of two address spaces: 0x4000_0000 - 0xFFFF_FFFF and 0x1_0000_0000 - 0x2_3FFF_FFFF. This configuration implies that DDR can be accessed using 32-bit and 64-bit addressing.
How are DDR memory locations addressed by each core?

A53 can access the regions from 0x1_0000_0000 to 0x2_3FFF_FFFF. Which is 0x1_0000_0000 to 0x1_FFFF_FFFF and 0x2_0000_0000 to 0x2_3FFFF_FFFF. If we add those numbers, we get ~4GB (0x1_0000_0000 → 0x1_FFFF_FFFF) + ~1GB (0x2_0000_0000 → 0x2_3FFF_FFFF) = ~5GB. Here is the 64-bit part, which is only accessible by A53. This makes sense if we take a look at the memory map:

5GB is the maximum addressable by core A53. The M4 core, on the other hand, can address memory from 0x4000_0000 to 0xFFFF_FFFF, which is the 32-bit part.

Now regarding how it’s being translated inside the processor, I’m not sure which device translates it and how it’s done. What we do know is that the DDR controller makes sure to differentiate the 0x1_0000_000 and 0x0000_0000 because they are different addresses (DDR and BOOTROM).

@ksalamun

Thirdly, how to explain the configuration in the device tree, where it says that the RAM address space is from 0x4000_0000 to 0x8000_0000?
This configuration implies that the first approach described above is relevant.
In this case, how is the access to DDR through the memory controller handled - is the DDR addressed by 32-bit addresses or are they translated to 64-bit addresses at some point?

The device tree specifies only the 32-bit part because the other 64-bit DDR is handled directly with the DDR controller. Probably if we take a look into the kernel drivers, the processor will communicate with the DDR controller to check how much memory is available and this information is going to be passed to the kernel dynamically.
Again, unfortunately, it’s hard to say how this is being translated/handled by the processor internally. We don’t have this type of information from NXP. You can ask about it directly at commnunity.nxp.com, so they can provide you with more information related to this part.

Best Regards,
Hiago.