Mallow carrier board Verdin-Am62 LVDS screen flickering

Technical Support
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Hi, I’m the Toradex AI Assistant.

I might make mistakes or occasionally get you wrong. Our support team will step in if needed.

Looking at your LVDS display issue with the Verdin AM62 SoM on the Mallow carrier board, I can help you troubleshoot the flickering and clock frequency problems you’re experiencing.

Root Cause Analysis

Based on the available documentation and your description, there are several potential causes for the flickering and clock frequency discrepancies:

1. Display Control Signals

The fact that your display works properly with the DSI-to-LVDS adapter but not with native LVDS suggests that control signals may not be properly configured (1). Native LVDS displays often require specific power-on sequences and control signals (such as RESET_N, DISPLAY_ON, or enable signals) that need to be properly managed through GPIO pins (1).

2. Data Mapping Configuration

Display flickering can be caused by incorrect data mapping settings (2). The data mapping determines how the RGB data is transmitted over the LVDS interface, and using the wrong mapping can cause visual artifacts (2).

3. Clock Domain Issues

The clock frequency discrepancy you’re observing (50MHz set vs 20MHz measured) indicates a potential issue with the clock configuration or pixel clock generation in the native LVDS path.

Troubleshooting Steps

Step 1: Verify Control Signals

Check if your display requires control signals and ensure they are properly configured as GPIOs in your device tree overlay (1). You may need to add GPIO control for signals like:

  • Display enable/power
  • Reset signals
  • Backlight control

Step 2: Review Data Mapping

Verify that your data-mapping property matches your display’s requirements (2). Common options include:

  • "jeida-18" or "jeida-24"
  • "spwg"
  • "vesa-24"

Step 3: Check Panel Timing Parameters

Ensure all timing parameters in your device tree match your display datasheet exactly (3). Pay particular attention to:

  • clock-frequency
  • hactive, vactive
  • hsync-len, vsync-len
  • Front and back porch values

Step 4: Validate Device Tree Structure

Your device tree overlay should follow the proper structure for native LVDS on Verdin AM62 (4). The overlay should configure the OLDI (LVDS) interface correctly and ensure proper port connections.

Device Tree Configuration Guidelines

When creating your device tree overlay, ensure you’re following the proper device tree structure and syntax (5). The device tree should include:

  1. Panel node with correct compatible string and timing parameters (3)
  2. Proper port connections between the panel and LVDS controller (5)
  3. GPIO configurations for any required control signals (1)
  4. Correct data mapping for your specific display (2)

Next Steps

Since I cannot see the specific content of your uploaded device tree file, I recommend:

  1. Compare with working DSI-to-LVDS configuration - Check what differs between the working DSI-to-LVDS setup and your native LVDS configuration
  2. Verify hardware connections - Ensure all required control signals are properly connected on your Mallow carrier board
  3. Test with reference overlay - Try using a reference LVDS overlay from the available pre-built overlays (4) as a baseline

The clock frequency discrepancy is particularly concerning and suggests a fundamental configuration issue with the LVDS clock domain that needs to be addressed at the device tree level.

Best regards, Toradex AI Assistant.

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