Please, check the overlay source code that you’re applying: verdin-imx8mm_hmp_overlay.dts « overlays - device-tree-overlays.git - Sources for Device Tree Overlays
This overlay disables the UART4, that’s why you can’t see it on the Linux side. This happens because this UART is used by default on the Cortex-M side to print debug messages on the NXP SDK.
[/quote]
Did you have a chance to review the attached file I uploaded? I made modifications to the UART configuration by changing the status to “okay.”
What issue did you face and what is your final objective?
I missed mentioning the output of the ls command in the /dev directory. After adding the overlay for SPI, I observed that there was no entry for spidev0.0 in the output.
Do you like to use the M4 Cortex to access the SPI?
No, I would like to use spidev0.0 with my DAC.
Allow me to describe the steps I took to enable second SPI spidev0.0 on TorizonCore 5:
In the imx8mm-verdin-dahlia.dtsi file, there is a pre-existing “Verdin SPI_1” interface that utilizes the “ecspi2” controller by default.
/* Verdin SPI_1 */
&ecspi2 {
status = "okay";
spidev20: spidev@0 {
compatible = "toradex,evalspi";
reg = <0>;
spi-max-frequency = <10000000>;
status = "okay";
};
};
I duplicated the existing code and made minimal modifications to create an SPI_2 controller device node labeled as “cspi1.”
/* Verdin SPI_2 */
&ecspi1 {
status = "okay";
spidev10: spidev@0 {
compatible = "toradex,evalspi";
reg = <0>;
spi-max-frequency = <10000000>;
status = "okay";
};
};
In the imx8mm-verdin.dtsi file, I made some modifications by utilizing the UART 2 pins to create a second SPI interface on the System-on-Module (SoM). These changes involved configuring the necessary pin assignments and making minor adjustments to the existing configuration. As a result, the SoM now has a secondary SPI interface available.
/* Verdin SPI_2 */
&ecspi1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_n>;
cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
status = "okay";
};
pinctrl_ecspi1_n: ecspi1grpn {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x6 /* SODIMM 137 */
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x6 /* SODIMM 139 */
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x6 /* SODIMM 41 */
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x6 /* SODIMM 143 */
>;
};
I tried to reproduce the steps on TorizonCore 6 by modifying the spi_1 configuration in the imx8mm_spidev_overlay.dts file…
/* Verdin SPI_1 */
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
spidev@0 {
/* Use compatible "rohm,dh2228fv" to bind spidev driver */
compatible = "rohm,dh2228fv";
reg = <0>;
spi-max-frequency = <10000000>;
};
};
/* Verdin SPI_2 */
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
spidev10: spidev@0 {
/* Use compatible "rohm,dh2228fv" to bind spidev driver */
compatible = "toradex,evalspi";
reg = <0>;
spi-max-frequency = <10000000>;
};
};
and applied similar modifications as done for imx8mm-verdin.dtsi. However, when checking the /dev/ output, it appears that there is no output for spidev0.0, and the modifications made to spidev0.0 did not take effect. 
I currently have two challenges: configuring UART4 and implementing a second SPI interface. I appreciate your assistance thus far.
Best regards,
Mehrdad
