IMX7D m4 core UART Baudrate problem

Technical Support
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1

I want to use uart for imx7d m4 core. When I do uart 5 as defined below, I miss a lot of packets. If I make the baudrate 115200 instead of 9600, it doesn’t miss. I have to do 9600 because of the structure of my circuit. Where could I be making a mistake? Can you help me?

Thanks in advance for the answers

RDC_SetPdapAccess(RDC, rdcPdapUart5, 0xFF, false, false);

CCM_UpdateRoot(CCM, ccmRootUart5, ccmRootmuxUartOsc24m, 0, 0);
CCM_EnableRoot(CCM, ccmRootUart5);

CCM_ControlGate(CCM, ccmCcgrGateUart5, ccmClockNeededAll);

configure_uart_pins(UART5);

// Setup UART init structure.
uart_init_config_t initConfig = {
.baudRate = 9600u,
.wordLength = uartWordLength8Bits,
.stopBitNum = uartStopBitNumOne,
.parity = uartParityDisable,
.direction = uartDirectionTxRx
};

initConfig.clockRate  = get_uart_clock_freq(UART5); //Uart5 for our board

UART_XFER_Config(UART5, &initConfig);

colibri IMX7D m4core uart baudrate 9600

2

Hi, I’m the Toradex AI Assistant.

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Hello! Thank you for your detailed question.

Based on your description, the fact that UART5 on the Colibri iMX7D M4 core works reliably at 115200 baud but misses packets at 9600 baud usually points toward a clock or configuration issue. Here are some points to check:

1. Clock Frequency for Baudrate Generation
At 9600 baud, the UART module needs a precise clock source—at least 16 times the target baudrate. That means your module clock should be at least 153.6 kHz. If the clock you set up via:

CCM_UpdateRoot(CCM, ccmRootUart5, ccmRootmuxUartOsc24m, 0, 0);

is not providing a precise enough frequency (or if the clock division isn’t accurate for 9600 baud, but works better for 115200), you may experience packet loss. Double-check the output of get_uart_clock_freq(UART5) and ensure it matches the requirements for 9600 baud. (Reference)

2. UART Configuration (Termios Settings / Initialization)
Ensure that your uart_init_config_t and related initialization covers all required parameters. Sometimes, buffer sizes or DMA settings can lead to missed bytes—especially at lower speeds.

3. DMA/Buffer Management
If DMA is enabled, it can introduce latency and potential loss at lower baud rates. Try to disable DMA for UART and use interrupt-based or polling RX/TX to see if reliability improves. (Reference)

4. Buffer Overrun/Underrun
If your code isn’t reading received bytes quickly enough, the receive buffer could overflow—especially at lower speeds where the hardware might not be triggering interrupts as often as expected. Make sure to monitor for overrun errors in your code.

5. Hardware Flow Control
If your hardware design permits, enable RTS/CTS hardware flow control. This can help manage situations where one side (the receiver) can’t keep up for a brief period. (Reference)

Summary of Actions:

  • Confirm the actual UART clock frequency and its divider for exact 9600 baud operation.
  • Disable DMA and use interrupt-driven RX/TX.
  • Check your RX buffer for overruns.
  • Consider hardware (RTS/CTS) flow control if necessary.

Relevant resources:

Would you like more detailed instructions about verifying your clock configuration or disabling DMA?
Best regards,
Toradex AI Assistant.

3

Haven’t you reparent your UART5 clock to something else than 24MHz oscillator clock? Since it is fine or almost fine at 115.2kBps and not fine at 9,6kBps, then perhaps your custom UART5 clock parent gets disabled periodically by some Linux driver, which in turn leads to comms problems?
24MHz oscillator is used by too many Linux drivers to get disabled. Take a look at your /sys/kernel/debug/clk/clk_summary to verify.

If not a clock issue, then did you scope your signals, perhaps something gets wrong physically at slow baud.

4

thanks for reply. I tried with other oscillator clock but it still didn’t work. Since the 24Mhz clock works fine with 115.2kBps, I don’t suspect linux