How to read MIPI CSI Register at Runtime UserSpace?

Hello All,
We have a MIPI CSI Camera OV5640 and Ixora and Apalis Imx8!!
I’m looking into checking the state of the Imx8 MIPI CSI Registers when I run gstreamer pipeline at userspace:

gst-launch-1.0 v4l2src device='/dev/video0' ! video/x-raw,format=YUY2,width=1920,height=1080,framerate=30/1 ! waylandsink -v

Is there a standard command(s) to find out MIPI CSI status register?

I want to check MIPI status register at runtime userpace, such as:
a. ECC and CRC Error Status Register
b. IRQ Status Register
c. ErrSot HS Status Register
d. ErrSotSync HS Status Register
e. ErrEsc Status Register
f. ErrSyncEsc Status Register
g. ErrControl Status Register

Can you please guide me?
Thank you in advance.

You can try to use dev/mem

Hello @alex.tx
Thank you for your answer.
I cant find some example for that ,right i dont have their physical register addrese !!
Can you guide me, if i want to write CSI block Register Status in the driver ,where can i do that??
in the /kernel-source/drivers/staging/media/imx/imx8-mipi-csi2.c/imx8-mipi-csi2.c( mxc_mipi_csi2_reg_dump(csi2dev) )

static void mxc_mipi_csi2_reg_dump(struct mxc_mipi_csi2_dev *csi2dev)
	struct device *dev = &csi2dev->pdev->dev;
	struct {
		u32 offset;
		const char name[32];
	} registers[] = {
		{ 0x100, "MIPI CSI2 HC num of lanes" },
		{ 0x104, "MIPI CSI2 HC dis lanes" },
		{ 0x108, "MIPI CSI2 HC BIT ERR" },
		{ 0x10C, "MIPI CSI2 HC IRQ STATUS" },
		{ 0x110, "MIPI CSI2 HC IRQ MASK" },
		{ 0x114, "MIPI CSI2 HC ULPS STATUS" },
		{ 0x118, "MIPI CSI2 HC DPHY ErrSotHS" },
		{ 0x11c, "MIPI CSI2 HC DPHY ErrSotSync" },
		{ 0x120, "MIPI CSI2 HC DPHY ErrEsc" },
		{ 0x124, "MIPI CSI2 HC DPHY ErrSyncEsc" },
		{ 0x128, "MIPI CSI2 HC DPHY ErrControl" },
		{ 0x180, "MIPI CSI2 HC IGNORE_VC" },
		{ 0x184, "MIPI CSI2 HC VID_VC" },
		{ 0x188, "MIPI CSI2 HC FIFO_SEND_LEVEL" },
		{ 0x18C, "MIPI CSI2 HC VID_VSYNC" },
		{ 0x190, "MIPI CSI2 HC VID_SYNC_FP" },
		{ 0x194, "MIPI CSI2 HC VID_HSYNC" },
		{ 0x198, "MIPI CSI2 HC VID_HSYNC_BP" },
		{ 0x000, "MIPI CSI2 CSR PLM_CTRL" },
		{ 0x004, "MIPI CSI2 CSR PHY_CTRL" },
		{ 0x008, "MIPI CSI2 CSR PHY_Status" },
		{ 0x010, "MIPI CSI2 CSR PHY_Test_Status" },
		{ 0x014, "MIPI CSI2 CSR PHY_Test_Status" },
		{ 0x018, "MIPI CSI2 CSR PHY_Test_Status" },
		{ 0x01C, "MIPI CSI2 CSR PHY_Test_Status" },
		{ 0x020, "MIPI CSI2 CSR PHY_Test_Status" },
		{ 0x030, "MIPI CSI2 CSR VC Interlaced" },
		{ 0x038, "MIPI CSI2 CSR Data Type Dis" },
		{ 0x040, "MIPI CSI2 CSR 420 1st type" },
		{ 0x044, "MIPI CSI2 CSR Ctr_Ck_Rst_Ctr" },
		{ 0x048, "MIPI CSI2 CSR Stream Fencing" },
		{ 0x04C, "MIPI CSI2 CSR Stream Fencing" },
	u32 i;


	dev_dbg(dev, "MIPI CSI2 CSR and HC register dump, mipi csi%d\n", csi2dev->id);
	for (i = 0; i < ARRAY_SIZE(registers); i++) {
		u32 reg = readl(csi2dev->base_regs + registers[i].offset);
		dev_dbg(dev, "%20s[0x%.3x]: 0x%.3x\n",
			registers[i].name, registers[i].offset, reg);

I found a function to debug register status , but it just shows the status when the start( mxc_mipi_csi2_reg_dump(csi2dev) ) !!

static int mipi_csi2_s_stream(struct v4l2_subdev *sd, int enable)
	struct mxc_mipi_csi2_dev *csi2dev = sd_to_mxc_mipi_csi2_dev(sd);
	struct device *dev = &csi2dev->pdev->dev;
	int ret = 0;

	dev_dbg(&csi2dev->pdev->dev, "%s: %d, csi2dev: 0x%x\n",
		__func__, enable, csi2dev->flags);

	if (enable) {
		if (!csi2dev->running++) {
	} else {
		if (!--csi2dev->running)


	return ret;

If i want to debug CSI register status at kernel mode as dynamic no just when the start ,where can i do that??
Thank you in advance.

Please refer to the i.MX 8QuadMax Applications Processor Reference Manual for HW addresses and other related details

Hello @alex.tx
Thank your for your answer.

I have an error at IRQ Status Register (CSI2RX_IRQ_STATUS) when log them.

31.065744] mxc_mipi_csi2_reg_dump
[ 31.069206] MIPI CSI2 HC num of lanes[0x100]:0x001
[ 31.074041] MIPI CSI2 HC dis lanes[0x104]:0x00c
[ 31.078633] MIPI CSI2 HC BIT ERR[0x108]:0x000
**[ 31.083075] MIPI CSI2 HC IRQ STATUS[0x10c]:0x028**
[ 31.087744] MIPI CSI2 HC IRQ MASK[0x110]:0x1ff
[ 31.092228] MIPI CSI2 HC ULPS STATUS[0x114]:0x000
[ 31.097002] MIPI CSI2 HC DPHY ErrSotHS[0x118]:0x000
[ 31.101969] MIPI CSI2 HC DPHY ErrSotSync[0x11c]:0x000
[ 31.107104] MIPI CSI2 HC DPHY ErrEsc[0x120]:0x000
[ 31.112140] MIPI CSI2 HC DPHY ErrSyncEsc[0x124]:0x000
[ 31.117256] MIPI CSI2 HC DPHY ErrControl[0x128]:0x000
[ 31.122334] MIPI CSI2 HC DISABLE_PAYLOAD[0x12c]:0x000
[ 31.127414] MIPI CSI2 HC DISABLE_PAYLOAD[0x130]:0x000
[ 31.132512] MIPI CSI2 HC IGNORE_VC[0x180]:0x000
[ 31.137298] MIPI CSI2 HC VID_VC[0x184]:0x000
[ 31.141680] MIPI CSI2 HC FIFO_SEND_LEVEL[0x188]:0x000
[ 31.146773] MIPI CSI2 HC VID_VSYNC[0x18c]:0x000
[ 31.151378] MIPI CSI2 HC VID_SYNC_FP[0x190]:0x000
[ 31.156144] MIPI CSI2 HC VID_HSYNC[0x194]:0x000
[ 31.160962] MIPI CSI2 HC VID_HSYNC_BP[0x198]:0x000
[ 31.165790] MIPI CSI2 CSR PLM_CTRL[0x000]:0x000
[ 31.170381] MIPI CSI2 CSR PHY_CTRL[0x004]:0x000
[ 31.174944] MIPI CSI2 CSR PHY_Status[0x008]:0x000
[ 31.179671] MIPI CSI2 CSR PHY_Test_Status[0x010]:0x000
[ 31.184870] MIPI CSI2 CSR PHY_Test_Status[0x014]:0x000
[ 31.190038] MIPI CSI2 CSR PHY_Test_Status[0x018]:0x000
[ 31.195199] MIPI CSI2 CSR PHY_Test_Status[0x01c]:0x000
[ 31.200354] MIPI CSI2 CSR PHY_Test_Status[0x020]:0x000
[ 31.205541] MIPI CSI2 CSR VC Interlaced[0x030]:0x000
[ 31.210530] MIPI CSI2 CSR Data Type Dis[0x038]:0x000
[ 31.215597] MIPI CSI2 CSR 420 1st type[0x040]:0x000
[ 31.220532] MIPI CSI2 CSR Ctr_Ck_Rst_Ctr[0x044]:0x000
[ 31.225622] MIPI CSI2 CSR Stream Fencing[0x048]:0x000
[ 31.230709] MIPI CSI2 CSR Stream Fencing[0x04c]:0x000

Based IMX8 TRM document,

0x10C, IRQ Status Register (CSI2RX_IRQ_STATUS) and based CSI Register Debug we have 0x28 value that fifth bit is equal bellow error(DPHY ErrSotSync_HS has occurred):

What does mean that??Can you guide me??

Thank you in advance.

Unfortunately, Toradex is not a member of the MIPI alliance, so we do not have access to the current MIPI CSI-2 specification. However, according to the draft spec I was able to find:
ErrSotSyncHS (Output): Start-of-Transmission Synchronization Error. If the high-speed SoT 1895 leader sequence is corrupted in a way that proper synchronization cannot be expected, this error is 1896 asserted for one cycle of RxByteClkHS.

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Thank you @alex.tx
your suggestion to debug this issue is very useful!!
Thanks for your help.

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