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The behavior you’re observing with the GPIO pin SODIMM_217 (GPIO4_IO14) is likely due to the System Controller Unit (SCU) and its firmware on the i.MX 8M Plus SoC. The SCU can override the default pin configurations set in the IOMUXC registers at boot time. This means that even though the reference manual indicates a reset state of 0x05 for GPIO mode, the SCU might be setting it to 0x04 (ENET1_RGMII_TD2 mode) as part of its default configuration.
To address this, you should verify the device tree configuration for your module. The device tree is responsible for defining the pin functions and should ensure that the pin is set to GPIO mode. Check the relevant device tree source files for any entries related to SODIMM_217 or GPIO4_IO14. Look for the fsl,pins property within the pin controller node, which specifies the pin’s function.
If the device tree does not explicitly set this pin to GPIO mode, you may need to modify it. You can add or adjust the device tree node to ensure the pin is configured correctly. This involves specifying the correct mux setting (0x05 for GPIO) in the device tree.
After making changes to the device tree, you’ll need to recompile it and deploy it to your module. This will ensure that the pin is configured as desired at boot time, overriding any default settings applied by the SCU.
This approach should resolve the discrepancy you’re seeing and allow the pin to function as a GPIO as expected. If you continue to experience issues, double-check the device tree settings and ensure that the correct configuration is being applied during the boot process.
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