Colibri imx6ULL UART_D (UART 6) not polulating by applaying patch

[mahi]

Hello community
Hope you all are doing well

I’m using Colibri i.mx6ULL som (512MB NAND version)
I’m using provided Yocto Kikrstone packages to generate the custom image

In my case, i have generate the custom image, and everything working as exacted
Now, my aim is to populate the UART_D i.e UART 6, for which i have created the 2 patches

one patch is with the “imx6ull-colibri.dtsi” file to de-reference the node for the UART 6, and one patch for the “imx6ull-colibri-eval-v3.dtsi” file to activate it!

For the instance, i need to use only TX pin to send the UART data for which, I’m utilizing SODIMM 75

To do so, i have also remove the shared functionality of this GPIO from the camera’s CSI port…

here is the UART_D node configuration

// with imx6ull-colibri.dtsi
/* Colibri UART_D */
&uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	fsl,dte-mode;
};

&iomuxc {
pinctrl_uart6: uart6grp {
		fsl,pins = <
			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x10b0 /* SODIMM 75 for the custom AEBOX image (UART_D)*/
		>;
	};
};
.
.
.
.
//with imx6ull-colibri-eval-v3.dtsi file 
&uart6 {
	status = "okay";
};

The image has been successfully generate. i have also verified that the patch is also successfully applied with the DTSI file with the kernel-source

Now my problem is, after booting with the new image, UART 6 is unable to populate in to the /dev directory

Can anyone help me here ?
Appreciate all comments and suggestions

I have attached both of the patch here [link]

Thanks
Mahendra

[ToradexAI]

Hi, I’m the Toradex AI Assistant. The Toradex Support team will follow up with you shortly!

Did you like my answer?

---

Based on the context provided, it seems you are trying to enable UART 6 on the Colibri iMX6ULL module by modifying the device tree files. You’ve made changes to the imx6ull-colibri.dtsi and imx6ull-colibri-eval-v3.dtsi files to configure and activate UART 6, specifically using the TX pin on SODIMM 75.

Here are a few suggestions to troubleshoot why UART 6 is not appearing in the /dev directory:

1. Check Device Tree Compilation: Ensure that the device tree source files are correctly compiled into the device tree blob (DTB) that is being used by the kernel. Verify that the DTB file is correctly updated on your target device.

2. Kernel Logs: Check the kernel boot logs (dmesg) for any messages related to UART 6. This can provide clues if there are any issues during the initialization of the UART.

3. Pin Multiplexing: Double-check the pin multiplexing settings in the iomuxc node. Ensure that the pin configuration for MX6UL_PAD_CSI_MCLK__UART6_DCE_TX is correct and not conflicting with other peripherals.

4. UART Driver: Ensure that the UART driver is enabled in the kernel configuration. The driver should be compiled and loaded correctly.

5. Device Tree Status: Confirm that the status of the UART 6 node is set to “okay” in all relevant device tree files.

6. Shared Functionality: Since you mentioned removing shared functionality from the camera’s CSI port, ensure that there are no residual configurations that might interfere with the UART functionality.

If these steps do not resolve the issue, you may need to provide more detailed logs or configuration files for further analysis.

Please, also check if these links can help you solve your problem:

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[sahil.tx]

Hi @mahi,
There is no need to re-compile image for modification in device tree.
You can compile the device tree outside of yocto by following this article.
After compiling, you can deploy the same and test.
Once you are ready with the device tree modification then you may add it to your yocto project.
Also, in case you need further help, please share the dtsi file in git diff format.

[mahi]

Hi… @sahil.tx
Thanks for the revert

i have attached the patch with my thread

pl. find the contents from here

diff --git a/imx6ull-colibri.dtsi.orig b/imx6ull-colibri.dtsi
index 336ab2e..7470071 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -60,6 +60,19 @@
 		};
 	};
 
+	p_req {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_preq>;
+
+		req0: user1 {
+			label = "p1_req";
+			gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; /* SODIMM 76 for custom AEBOX image*/
+			default-state = "off";
+			linux,default-trigger = "mmc0";
+		};
+	};
+
 	panel_dpi: panel-dpi {
 		compatible = "edt,et057090dhu";
 		backlight = <&backlight>;
@@ -296,6 +309,13 @@
 	fsl,dte-mode;
 };
 
+/* Colibri UART_D */
+&uart6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart6>;
+	fsl,dte-mode;
+};
+
 /* Colibri USBC */
 &usbotg1 {
 	dr_mode = "otg";
@@ -450,7 +470,7 @@
 	pinctrl_gpio2: gpio2grp { /* Camera */
 		fsl,pins = <
 			MX6UL_PAD_CSI_DATA04__GPIO4_IO25	0x10b0 /* SODIMM 69 */
-			MX6UL_PAD_CSI_MCLK__GPIO4_IO17		0x10b0 /* SODIMM 75 */
+			/* MX6UL_PAD_CSI_MCLK__GPIO4_IO17		0x10b0 SODIMM 75 */
 			MX6UL_PAD_CSI_DATA06__GPIO4_IO27	0x10b0 /* SODIMM 85 */
 			MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18	0x10b0 /* SODIMM 96 */
 			MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x10b0 /* SODIMM 98 */
@@ -638,6 +658,12 @@
 		>;
 	};
 
+	pinctrl_uart6: uart6grp {
+		fsl,pins = <
+			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x10b0 /* SODIMM 75 for the custom AEBOX image (UART_D)*/
+		>;
+	};
+
 	pinctrl_usbh_reg: usbhreggrp {
 		fsl,pins = <
 			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x10b0 /* SODIMM 129 / USBH_PEN */
@@ -710,6 +736,12 @@
 			MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
 		>;
 	};
+
+	pinctrl_gpio_preq: gpiopreq {
+		fsl,pins = <
+			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00     0x00079  /* SODIMM 76 for AEBOX P1-REQ signal*/
+		>;
+	};
 };
 
 &iomuxc_snvs {

the contents for the 2nd patch is here

diff --git a/imx6ull-colibri-eval-v3.dtsi.orig b/imx6ull-colibri-eval-v3.dtsi
index 692ef26..a347143 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -105,6 +105,10 @@
 	status = "okay";
 };
 
+&uart6 {
+	status = "okay";
+};
+
 &usbotg1 {
 	disable-over-current;
 	vbus-supply = <&reg_usbh_vbus>;

pl. let me know anything further required

Thanks

[sahil.tx]

Hi @mahi ,
I am not sure why there is only one pin(only rx) in your UART.
Test with the following modification

&uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	fsl,dte-mode;
	status = "okay";
};
pinctrl_uart6: uart6grp {
		fsl,pins = <
		        MX6UL_PAD_CSI_MCLK__UART6_DTE_RX        0x1b0b1
                        MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX      0x1b0b1
		>;
	};

Additionally, comment out SODIMM 75 and SODIMM 96 in pinctrl_gpio2: gpio2grp.
Compile the device tree and test.