We’re have designed a custom carrier board which hosts the apalis imx6 quad core module. Now redesign is in progress in order to get better signal integrity and EMI compliance on the CSI interface. Some hints on signal routing are found on the Apalis datasheet (table 5.64). One is to match impedance at 50R, as better explained in another post (Apalis Parallel CSI Impedance Matching - Toradex Community).
Another one is to equalize the signal lines and limit the skew to 1ps or 10ps. This implies to control the line length to 0.15mm. My questions are about how to achieve this, because we can control just the length from the signal source to the module edge, and nothing is specified on what happens on the module.
- Can we assume that the CSI lines are already equalized inside the module so that we just have to take care of the equalization on the carrier?
- If NO: what is the module-related delay we have to compensate by adjusting the length on the carrier?
- if YES: is it possible to know what is the length of the lines on the module (edge - to imx6 ball)?
Thank you in advance,