I have reviewed the datasheet for the Toradex 1212 10.1 display from Logic Technologies, LT170410-2WHC. the Datasheet doesn’t identify the Source driver with LVDS interface. I’m using this display in relationship to the Dahlia Carrier Board with the i.MX8MP SoM.
I’m currently comparing the DTSI file of this display to a new display using a FIT EK79202B driver IC. Currently the new display is experiencing a vertical syncing issue and I’m trying to identify root cause as it might be related to the display configuration.
Display Comparison
Column 1
Column 2
C
D
E
F
Column 3
H
Column 4
J
Logic Technologies
NEW
LT170410-2WHC
xxxxxx
LVDS - 4 Channel
LVDS 4 Channel
Clock Frequency
1/Tc
68.9
71.1
73.4
68.2
72.4
78.5
Horizontal Display Area
tHD
1280
1280
HS period time
tH
1410
1440
1470
1380
1440
1500
HS Front Porch
tHFP
12
72
132
HS Back Porch
tHBP
88
88
88
HS Width
tHW
-
-
-
HS Width + BP + FP
tHW+tHBP+tHFP
60
160
190
100
160
220
Vertical display area
tVD
800
800
VS Period time
tV
815
823
833
824
838
872
VS Front Porch
tVFP
1
15
49
VS Back Porch
tVBP
23
23
23
VS Width
tVW
-
-
-
VS Width + BP + FP
tVW+tVBP+tVFP
15
23
33
24
38
72
DTSI File
Column 1
Column 2
Column 3
Column 4
E
F
G
H
DTSI File
DTSI Update
Original
New Display
68.9
71.1
73.4
68.2
72.4
78.5
1280
1280
1341
1440
1469
1380
1440
1500
23
60
71
10
70
130
23
60
71
88
88
88
15
40
47
2
2
2
61
160
189
100
160
220
800
800
816
823
832
824
838
872
5
7
10
9
13
47
5
7
10
13
23
23
6
9
12
2
2
2
16
23
32
24
38
72
Looking for input on the display comparison and how best approach for the display panel integration including modification of the DTSI file.
The External TI MIPI_LVDS bridge IC can generate a stable image at both display targets, the Logic Technologies and the new display.
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Hello! Thank you for sharing such detailed information. I understand you’re integrating a new LVDS panel (with FIT EK79202B driver IC) into your Verdin iMX8M Plus on the Dahlia Carrier Board and are having vertical sync issues, while your LT170410-2WHC panel is functioning correctly.
Let’s break down the best approach for stable LVDS integration and necessary DTSI (device tree) adjustments:
1. Understand the Critical Device Tree Parameters
LVDS panel timing parameters in the device tree must precisely match those specified by your new panel’s datasheet. Key fields for a typical LVDS panel are:
clock-frequency (in Hz)
hactive, vactive (horizontal/vertical resolution)
hsync-len, hfront-porch, hback-porch
vsync-len, vfront-porch, vback-porch
Color mapping/data mapping (fsl,data-mapping, data-mapping)
You’ll configure these within the display-timings node of your overlay.
2. Map Datasheet Parameters to Device Tree Fields
Referencing your tables, you’ll want to extract timing fields for the NEW display:
LCD Timing
Device Tree Field
Value (typical or mid-range based on your table)
Pixel Clock Frequency
clock-frequency
72,400,000 (for 72.4 MHz for new display)
Horizontal active (pixels)
hactive
1280
Horizontal total (tH)
hactive + hfront + hback + hsync
1440
Vertical active (lines)
vactive
800
Vertical total (tV)
vactive + vfront + vback + vsync
838
For porch and sync calculation:
hblank = total - active
vblank = total - active
Assign values to hsync-len, hfront-porch, and hback-porch based on proportions in datasheet or, if given, direct values.
Assign values to vsync-len, vfront-porch, and vback-porch similarly.
Example Calculation (if values are given as in your table):
Make sure your device tree overlay is being applied (check /proc/device-tree/).
If timings seem correct but image is unstable, tweak the sync and porch settings by small increments, as LVDS panels can be sensitive to these margins.
Confirm clock-frequency matches within the datasheet’s allowed range.
If the TI MIPI-LVDS bridge works but direct mode does not, it’s likely timing or color mapping, not hardware.
Ensure the LVDS interface is in 4-channel mode if your panel requires this.
Summary of Integration Steps
Align the device tree timings (including sync and porch) to the new panel datasheet.
Set the appropriate color/data mapping (jeida-24, vesa-24, or as per your panel).
Test and fine-tune: Start with datasheet mid-values; adjust porch/sync if you see jitter, tearing, or sync loss.
Let me know if you want a ready-to-use overlay based on the exact datasheet specs, or if you have the direct register/timing details for the new panel!
LVDS is a high-speed digital signaling standard, so you don’t need a dedicated driver for the display IC itself. Instead, you need an LVDS driver for the i.MX8M Plus SoC, and it should be configured to match the display’s parameters—such as resolution, pixel clock, sync timings, signal polarity, etc.
I am using the overlay.txt file is how I am changing the display configuration using the overlay method described within the link provided. The tables provided is the configuration difference between the Toradex evaluation display 1212 and the display that has been chosen for this integration platform. I modified the “display-lt170410_sn65dsi84_overlay.dtsi” file and had that recompiled for the evaluation platform. Also changing the overlay.txt file enabled the overlay and enabled the display VIA the Texas Instruments SN65DSI84 MIPI-LVDS bridge.
Reference I’m using the following evaluation image Toradex Embedded Linux Reference Multimedia Image 7.3.0+build.8 (2025-7-03)
I put that file into the boot directory and changed the overlay.txt file to include the verdin-imx8mp_dsi-to-lvds_panel-cap-touch-10inch-lvds_overlay.dtbo
Due to the bridge being able to generate a stable test image I believe that the source is the dataset being sent to the MIPI-LVDS bridge. We have tried the new .dtsi file in the above table but with no change to the failure mode.
Note: I tried uploading the .dtsi file and the a video of the evaluation platform with both displays active, but the system won’t allow me due to being a new user for reference on the issue.