LVDS1_B single mode

Technical Support
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1

Dear all,

i’m working with the following configuration:
Apalis iMX8QM 4GB WB IT V1.1D
Ixora Carrier Board V 1.2A
DISTRO_VERSION = “6.8.2”
DISTRO_CODENAME = “krikstone”

10.1 I am trying to connect LCD(RGB666) to Ixora carrier board.
I want to connect LVDS1_B without using LVDS1_A (single mode)
I am writing device tree overlay:

 &ldb2 {                                                         
     status = "okay";                                            
                                                                 
     lvds-channel@0 {                                            
         status = "disabled"; // LVDS1_A OFF                      
     };                                                          
                                                                 
     lvds-channel@1 {                                            
         reg = <1>;                                              
         fsl,data-mapping = "spwg";                          
         fsl,data-width = <18>;                                  
         status = "okay";                                        
                                                                 
         port@1 {                                                
             reg = <1>;                                          
                                                                 
             lvds1b_out: endpoint {                              
                 remote-endpoint = <&panel_lvds_in>;             
             };                                                  
         };                                                      
     };                                                          
 };                                                              

&panel_lvds {                                                       
    data-mapping = "jeida-18"; // jeida-18bit panel
    height-mm = <136>;                                              
    width-mm = <217>;                                               
    status = "okay";                                                
                                                                    
    panel-timing {                                                  
        clock-frequency = <72400000>;                               
        de-active = <1>;                                            
        hactive = <1280>;                                           
        hback-porch = <88>;                                         
        hfront-porch = <72>;                                        
        hsync-active = <0>;                                         
        hsync-len = <40>;                                           
        pixelclk-active = <1>;                                      
        vactive = <800>;                                            
        vback-porch = <20>;                                         
        vfront-porch = <18>;                                        
        vsync-active = <0>;                                         
        vsync-len = <9>;                                            
    };                                                              
                                                                    
    port {                                                          
        panel_lvds_in: endpoint {                                   
            remote-endpoint = <&lvds1b_out>;                        
        };                                                          
    };                                                              
};

The colors on the LCD appear as follows:

KakaoTalk_20250422_171534711
KakaoTalk_20250422_1715347111920×1155 506 KB

Can you help me to solve this problem?

Best regards,
sjjin

2

Hi, I’m the Toradex AI Assistant. The Toradex Support team will follow up with you shortly!

Did you like my answer?

:+1: :-1:

Hello! When working with LVDS displays on Toradex hardware, there are several key layout requirements to keep in mind:

  • The trace impedance should be 100Ω ±15% differential and 50Ω ±15% single-ended.
  • Maximum intra-pair skew should be less than 1 picosecond (ps).
  • Maximum trace length skew between clock and data pairs should be less than 3.5 picoseconds.
  • Maximum trace length on the carrier board and display cable should be less than 500 millimeters.
  • Minimum pair-to-pair spacing should be greater than twice the intra-pair spacing.

For configuring LVDS1_B in single mode without LVDS1_A, specific documentation might not be readily available. However, you can explore the following resources for guidance:

  1. Review the device tree documentation specific to your i.MX 8 module, as it may contain relevant configuration details.
  2. Consult the i.MX 8 reference manual, which often includes comprehensive information on LVDS configuration options.

If you need further assistance, I can provide a general approach for LVDS configuration based on available documentation.

Feel free to reach out if you have more questions!

Best regards, Toradex AI Assistant.