What is the purpose of 1588 event input/output ? What is the purpose of 1588 specific PHY?

We’ve been developping an acquisition system with a Colibri iMX7 for more than a year. IEEE 1588 time synchronization is part our products specifications. I tested PTP protocol with several hardware devices. The IEEE 1588 time synchronization works well with Colibri but the software variant implementation. I’m waiting a second demo board to test the hardware version.

We’ve seen several 1588 event lines. They are not used by the KSZ8041 phy. I’m wondering theirs purpose.
At the the page 2909, they have written this for the input:

Capture/compare block input/output
event bus signal. When configured for
capture and a rising edge is detected,
the current timer value is latched and
transferred into the corresponding
ENET_TCCRn register for inspection by
software. When configured for compare,
the corresponding signal 1588_EVENT is
asserted for one cycle when the timer
reaches the compare value programmed
in register ENET_TCCRn. An interrupt
or DMA request can be triggered if the
corresponding bit in ENET_TCSRn[TIE]
or ENET_TCSRn[TDRE] is set.

And this for the output:

Capture/compare block input/output
event bus signal. When configured for
capture and a rising edge is detected,
the current timer value is latched and
transferred into the corresponding
ENET_TCCRn register for inspection by
software. When configured for compare,
the corresponding signal 1588_EVENT is
asserted when the timer reaches the
compare value programmed in register
ENET_TCCRn. An interrupt or DMA
request can be triggered if the
corresponding bit in ENET_TCSRn[TIE]
or ENET_TCSRn[TDRE] is set. NOTE:
ENET_1588_EVENT0_OUT has a
programmable output width, see
IOMUXC_GPR0[CLK_STRETCH], delayed one
clock cycle in relation to all other
EVENTx_OUT signals.

I have seen 1588 examples without using those lanes. So I assume they are not mandatory.

We are looking for a PHY to use it as seccond network interface. We are thinking to substitute the KSZ8041 with the KSZ8441. KSZ8441 - Ethernet Controllers . Very similar to the the KSZ8041, it has embedded 1588 timers embedded. I don’t know what would bring this PHY in addition.

[upload|4fmdTvnqezEf1WIdzGRjRAQl9Hw=]
[upload|5O4iwIiq9oHsLv9SKjj87iszgQg=]

I didn’t test physical PTP yet, but I was wondering why they are 1588 specific PHY with 1588 specific lanes and incorporated timers.

It depends on what kind of time synchronization requirement you have.
There are the IEEE-1588 Hardware and software on plus there is time synchronization based on the TSN standard 802.1AS. A TSN able controller can usually also support IEEE-1588 hardware synchronization.

here something on the IEEE-1588 background.

Did you want to send a link by writing “here something on the IEEE-1588 background.” ?

Sorry, I forgot. https://www.silabs.com/whitepapers/ieee-1588-standard

It’s not urgent, but do you have any news ? Did you ask any third party to get any answer (NXP) ?

Let me know as soon as you get any news ! I’m looking forward to getting any additional information.

Hello arnaud,

What new are you waiting for ?

Best Regards,

Matthias Gohlke

Hello Matthias,

If I will get any answer. If you gave up, it wouldn’t be a big deal. I will keep going on our project without knowing the 1588 Event lane purpose.

I just got a working 1588 synchronization now. So I can close the ticket without answer.

Hello arnaud,

it was just not clear to us what you are waiting for. So its the 1588 Event lane purpose you want to know