We’ve been developping an acquisition system with a Colibri iMX7 for more than a year. IEEE 1588 time synchronization is part our products specifications. I tested PTP protocol with several hardware devices. The IEEE 1588 time synchronization works well with Colibri but the software variant implementation. I’m waiting a second demo board to test the hardware version.
We’ve seen several 1588 event lines. They are not used by the KSZ8041 phy. I’m wondering theirs purpose.
At the the page 2909, they have written this for the input:
Capture/compare block input/output
event bus signal. When configured for
capture and a rising edge is detected,
the current timer value is latched and
transferred into the corresponding
ENET_TCCRn register for inspection by
software. When configured for compare,
the corresponding signal 1588_EVENT is
asserted for one cycle when the timer
reaches the compare value programmed
in register ENET_TCCRn. An interrupt
or DMA request can be triggered if the
corresponding bit in ENET_TCSRn[TIE]
or ENET_TCSRn[TDRE] is set.
And this for the output:
Capture/compare block input/output
event bus signal. When configured for
capture and a rising edge is detected,
the current timer value is latched and
transferred into the corresponding
ENET_TCCRn register for inspection by
software. When configured for compare,
the corresponding signal 1588_EVENT is
asserted when the timer reaches the
compare value programmed in register
ENET_TCCRn. An interrupt or DMA
request can be triggered if the
corresponding bit in ENET_TCSRn[TIE]
or ENET_TCSRn[TDRE] is set. NOTE:
ENET_1588_EVENT0_OUT has a
programmable output width, see
IOMUXC_GPR0[CLK_STRETCH], delayed one
clock cycle in relation to all other
EVENTx_OUT signals.
I have seen 1588 examples without using those lanes. So I assume they are not mandatory.
We are looking for a PHY to use it as seccond network interface. We are thinking to substitute the KSZ8041 with the KSZ8441. https://www.microchip.com/wwwproducts/en/KSZ8441 . Very similar to the the KSZ8041, it has embedded 1588 timers embedded. I don’t know what would bring this PHY in addition.
[upload|4fmdTvnqezEf1WIdzGRjRAQl9Hw=]
[upload|5O4iwIiq9oHsLv9SKjj87iszgQg=]
I didn’t test physical PTP yet, but I was wondering why they are 1588 specific PHY with 1588 specific lanes and incorporated timers.