Watchdog for iMX8M-Plus

In i.MX 8M Plus Applications Processor Reference Manual from NXP I see that iMX8M-Plus has 3 watchdog timers.

They’re described in paragraph 6.6 of the PRM itself.
On Toradex KB I find this article that doesn’t refer to the Plus (i.MX 8M Mini is there).
And so I suppose one of the watchdog timers is (can be) used by Linux that runs on Cortex-A (A53).

  • is this watchdog timer used by TorizonOS?
  • which is the timer used for Linux (WDOG1, WDOG2 or WDOG3)?
  • in PRM I see that pin B6 (GPIO1_IO02) can be configured to be triggered for WDOG1_WDOG_ANY or WDOG1_WDOG_B. Is this pin available on Verdin X1 connector? It doesn’t seem so from the datasheet, but I need a confirmation.

In my project I use Cortex-M too and so I need to use a dedicated watchdog for it.
The wdog example from NXP SDK uses WDOG3 for Cortex-M.

  • Can I use it on Verdin SoM too?
  • Does this resets Cortex-M only?
  • Is the Cortex-M firmware preserved? Or should the Cortex-A take care of reloading it?

Thanks in advance

Hello @vix,
Here are the answers I could find to your questions:

which is the timer used for Linux (WDOG1, WDOG2 or WDOG3)?

Our standard device-tree selects WDOG1 to be used by linux:
https://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi?h=toradex_5.15-2.2.x-imx#n1003

is this watchdog timer used by TorizonOS?

I would assume yes, the standard device-trees remain the same in Torizon

in PRM I see that pin B6 (GPIO1_IO02) can be configured to be triggered for WDOG1_WDOG_ANY or WDOG1_WDOG_B. Is this pin available on Verdin X1 connector? It doesn’t seem so from the datasheet, but I need a confirmation.

You can see that this pin is configured by default in our device-tree to WDOG1_WDOG_B:
https://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi?h=toradex_5.15-2.2.x-imx#n1522

The extra flag fsl,ext-reset-output; on the watchdog device-tree node means that the watchdog will not generate a software reset, but will instead assert the WDOG_B pin. This pin is not available on the edge connector, it’s connected to the PMIC.

Can I use it on Verdin SoM too?
Does this resets Cortex-M only?

As you can see on the RM, there are options to configure WDOG3 to either reset only the M7 or the full system:

Is the Cortex-M firmware preserved? Or should the Cortex-A take care of reloading it?

I think this would need to be tested and I imagine it could also depend on which memory you’re linking your M7 code to. If resetting only the M7 core, I would think the memories (like TCM) should not be reset with it because the entire chip is not going through a reset. So it could be that the M7 would just start running as if the firmware was on flash. The NXP WDOG example you pointed seems to also point in this direction.

Best regards,
Rafael

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