I have a problem with LCD display model PV0700JW50C resolution 800x480, (LDDS 24), digital transfer . Like you can see on my pictures screen can display file name correctly when is more like 3 lines and when I move cursor to one of the screen side the whole line is shifted.
My register configuration is :
All displays sample eack pixel according to the PCLK signal.
Your pictures show a situation where the display samples the pixel colors just in the moment while they are transitioning from one pixel to the next. The sampling point is given by the PCLK signal. Depending on the actual signal waveforms, sometimes the previous pixel is sampled, sometimes the next one.
Probably inverting the pixel clock polarity (PCP) will fix the issue.
If not, you can try to play with the buffer strength (LCDBS) to create a small analog delay of the signals. Adding a small capacitor to the PCLK signal could have the same effect. I recommend to measure the signals with an oscilloscope to get an understanding what you are doing.
Hi Andy,
Spot on working fine! PCP did the job but I can’t change it with Vybrid_Display_V1.0 Win app I had to change on my boot config block settings section.
Just like you said I measure the signal with oscilloscope was very helpful.
