VF61 uart ports pinouts

I am confused about the pinouts of the VF61 Uart ports. The schematic of the Colbri Evaluation Board clearly shows Uart A using 8 signals- DTR on pin 23, CTS on pin 25, RTS on pin 27, DSR on pin 29, DCD on pin 31, RXD on pin 33, TXD on pin 35, and RI on pin 37. According to the colibri_vf50_vf61_pinout.xlsx spreadsheet, these pins are the following: DTR is PTA20, CTS is PTB13, RTS is PTB12, DSR is PTA31, DCD is PTA21, RXD is PTB11, TXD is PTB10, and RI is PTA30.

Then I use the Toradex Pinout Designer tool and I see there are only 4 signals listed under UART_A. I see CTS, RTS, RX, and TX. However, there is nothing listed for DTR, DSR, DCD, or RI.

In my application I would like to use UART_E as a simple 2 wire serial interface using RXD and TXD. However, the pinout designer shows that UART_E RX may only be assigned to PTA31 or PTA21. Both of these signals are being used by the UART_A console port interface on the evaluation board. Also, UART_E TX may only be assigned to PTA20 or PTA30. Both of these signals are also being used by the UART_A console port on the evaluation board.

Next I looked at the device tree files for the Colibri VF61. I see there are actually 6 Uarts defined (numbered 0-5), even though the pinout design tool shows only 5 Uarts (A-E). And in the device tree file Uart0 is defined to use only 4 pins (TX on PTB10, RX on PTB11, RTS on PTB12, and CTS on PTB13). I find PTA20, PTA21, PTA30, and PTA31 listed in pinctrl_hog_0, apparently as GPIO pins if I understand correctly. But I don’t know what a “hog” is in the device tree!

So my question is, are the DTR, DSR, DCD, and RI signals on pins PTA20, PTA31, PTA21, and PTA30 actually used by the UART_A console port or not? Are they really just GPIO pins, and are they even used at all by the Linux console? The Toradex pinout designer leads me to believe that these pins can be used by the UART_E interface, but I don’t want to commit to the design of a printed circuit board for my project until I am sure.

Help, any information would be greatly appreciated. I am confused. The Colibri Evaluation Board schematic shows UART_A_DTR (SODIMM_23, or PTA20), UART_A_DSR (SODIMM_29, or PTA31), UART_A_DCD (SODIMM_31, or PTA21), and UART_A_RI (SODIMM_37, or PTA30) all connected to the UART_A console port. Yet the Toradex Pinout Designer makes no mention of these signals for UART_A, but in fact shows PTA20, PTA21, PTA30 and PTA31 as the only available pins to use for UART_E. So are these signals really being used by the UART_A linux console port or not? Can I safely use these pins for UART_E? I need an answer here.

Hi @irbsd,

Please apologize the late answer. It can be a little bit confusing. I have tried to clarify it in our datasheet in section 5.9 on page 36. The Apalis standard itself features in total 3 UART interfaces of which the first one (UART_A) is a full featured with a total of 8 pins. However, the VFxx SoC only features UART interfaces with maximum 4 pins (only hardware handshake, no DTR, DSR, DCD, and RI). We have placed regular GPIO pins on these module edge connector pins. One can either use these GPIO pins for bit banging the additional UART signals or alternately use all the other functions of the IO pins.

The SoC has a total of 5 UARTs that are available externally. Three of them are available as standard UARTs (A to C). The additional two UARTs are available as alternate functions of IO pins. As you have seen, the UART_E (this is the original SCI3 UART port of the SoC) is available on the pins 29 or 31 respectively 23 or 37. The original standard function of the pins 29, 31, 23, and 37 is the additional DTR, DSR, DCD, and RI of UART_A. As written above, the SoC does not feature these functions. Therefore, you can use the pins as UART_E without problems. Just keep in mind, only the first 3 UARTs are compatible with other Colibri modules.

On the Evaluation board, only the standard interfaces are having real world connectors. Therefore, only the first 3 UARTs are having a transceiver and connectors on the carrier board. However, there is a jumper area. This hallows you to disconnect an interface from its original real world connection and use jumper wires for using a pin for other purposes. This allows you to test the UART_E on the evaluation board.