VF61 I2S confusion

In the VF61 datasheet, on page 49, table 5-32, five signals are listed for using an I2S codec on the SAI interface. SCLK, DOUT, LRCLK, DIN and MCLK

However, on the Toradex Pin designer software, for the DIGITAL_AUDIO_2 port, when we select DIGITAL_AUDIO_I2S_MASTER, only 4 pins gets selected (DIN, DOUT, LRCLK and SCLK).

Is there a reason why MCLK not listed on the I2S interface in the pin designer?

MCLK is the clock that is used by the audio codec to time and/or drive its own internal operation. Not all converters require this clock. So I think this is the reason that this signal was not listed in pin designer.

Take a look at http://cache.freescale.com/files/microcontrollers/doc/AN4486.pdf item 4.1.

Exactly, the audio codec’s master clock (if there is any at all) has per se nothing to do with resp. digital audio interface e.g. I2S in your case. However to lower component count and for synchronisation reason it might be desirable to drive an audio codec directly off a SoC internal audio PLL which might be available on some external clock pins.