Hello,
Currently we are working with a custom carrier board using the Verdin IMX8M plus SoM. As we need a second Ethernet, there is a LAN8720A RMII PHY connected to the SoM using the signals described in the Verdin IMX8M-Plus datasheet in Table 5.9. But we have some trouble getting it to work.
The 50Mhz clock is created by the SoM using this change in U-boot in the file “board/toradex/verdin-imx8mp/verdin-imx8mp.c”
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Enable RGMII TX clk output */
setbits_le32(&gpr->gpr[1], BIT(13));
return set_clk_enet(ENET_50MHZ);
}
The device tree for the RMII phy is the following:
/* Verdin ETH_2_RMII */
&fec {
phy-handle = <ðphy1>;
assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
<&clk IMX8MP_CLK_ENET_TIMER>,
<&clk IMX8MP_CLK_ENET_REF>,
<&clk IMX8MP_CLK_ENET_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_50M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <50000000>,<5000000>;
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
smsc;
};
};
};
The 50Mhz out works, and the SoM communicates via the MDIO interface with the PHY. It shows up as Eth0. When I connect a cable to a computer, the link detect works and the PHY communicates to the SoM that a cable is plugged in.
The problem currently is that the SoM does not communicate using the RD0/RD1/TD0/TD1
There is data from the PHY going to the SoM on the RD0/RD1 lines but the phy seems to ignore that and the TD0 and TD1 line remain a logic low.
It seems that there might be something not correct in the device tree as the SoM does not try to communicate with the PHY, I hope you can give us some pointers?
Rik
