We have a GPIO connected to Pin 42 (I2S_2_BCLK, GPIO5_IO0) of Verdin iMX8M-Plus Module v1.0C
In the device tree it is configured as simple IO like below /* 0x096 (PE_0_PULL_DISABLE | HYS_1_SCHMITT | PUE_0_WEAK_PULL_DOWN | ODE_0_OPEN_DRAIN_DISABLE | FSEL_1_FAST_SLEW_RATE | DSE_X6) */
On the pin, we have also an external 10kohm pullup goes to 1.8V rail. It works fine, we can set or clear the output. Or when we want to read, it reads as logic-1 through external pull up. Perfect.
The problem is when we reset the SoM through Reset switch or with the reboot command in the console, the IO generates a low pulse for about 250ms during reboot. This is a problem for us. We expect it to stay high over the external pullup during the reboot.
I also observed that if I keep reset button of the SoM pressed, I see a logic-0 all the time on the pin over a scope. Note that 1.8V is always stable during the reset.
What shall we expect for the GPIO states during the reset or in the reset (keep reset button pressed)?
Do make sure that same pin is not configured in uboot device tree. If u-boot has that pin configured s GPIO or peripheral then you would see this glitch.
I would make same change to uboot device tree same as you mentioned here for kernel device trees for that GPIO line.
Can you confirm that mentioned “low pulse” happens during U_boot phase (before OS loading) ?
And if you have pin 42 pulled up externally why do you use PUE_0_WEAK_PULL_DOWN ?
Can you confirm that mentioned “low pulse” happens during U_boot phase (before OS loading) ?
Thank you @alex.tx. I will check that tomorrow. But more interesting problem is that when I hold reset button as pressed. In this case, the IO directly goes to zero and sticks there until I release the reset button back.
As I know, when I keep the reset button pressed, neither u-boot nor the linux is being active.
And if you have pin 42 pulled up externally why do you use PUE_0_WEAK_PULL_DOWN ?
Since PE_0_PULL_DISABLE is defined, PUE_0_WEAK_PULL_DOWN or UP are not important. I keep it in the comment to understand which bit is what.
The GPIO block of iMX8M plus get powered by same power rail as PWR_1V8_MOCI. And according to Verdin standard this rail is set low in case of reset. Please check chapter 3.3 General Power Sequences of Verdin Carrier Board Design Guide for details.
Could you please specify which exactly 1.8V you are referencing?
Are you using Toradex carrier board or a custom one?
So with the reset button, it gets cold reset. This explains the behavior we have on the board. Linux reboot command has the similar effect as well. That case we observe a low pulse about 250ms.
I made all my tests on our custom carrier board. There we don’t use PWR_1V8_MOCI output of the SOM, we have an external 1V8 regulator which is not controlled by CTRL_PWR_EN_MOCI pin on purpose and which pull ups are connected to.
Is there a way of doing warm reset for the Verdin iMX8M-Plus? We don’t want to lose power rails during the reset.
Warm reset means → Just rise the reset pin of the processor without touching the power rails
Cold reset means → Full power down and up
What we want simply is that GPIO states should keep their positions during the warm reset.
For example, if some of the IOs are adjusted to be output 1 while running, they should remain as output-1 during the warm reset according to iMX8M-Plus Reference Manual.
As for the warm reset, I guess it will come down to making sure that the GPIO’s in question are not touched by u-boot and also not hogged by the linux kernel initialization. I’m not completely sure if the gpio initialization phase forces a specific state on the GPIO’s
We have this property on the device trees called “gpio-hog”. It sets the state of the GPIO to the predefined value on initialization.
have you checked there?
