Hi @henrique.tx,
I managed enabling ecspi1 in the u-boot environment and FPGA configuration worked very well.
-
I added spi1 = &ecspi1; as alias in imx8mp-verdin.dts. Because alias spi0 is already defined in imx8mp.dtsi as spi0 = &flexspi; This should solve the error you have.
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I had to configure pads in the board/toradex/verdin-imx8mp/verdin-imx8mp.c and ecsp1 clocks in drivers/clk/imx/clk-imx8mp.c. I think DTS definitions are ignored in this context, the correct configuration must be in the code.
In verdin-imx8mp.c:
#ifdef CONFIG_MXC_SPI
#define SPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
static iomux_v3_cfg_t const ecspi1_pads[] = {
MX8MP_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX8MP_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX8MP_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX8MP_PAD_ECSPI1_SS0__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
//gpio_request(IMX_GPIO_NR(5, 9), "ECSPI1 CS");
init_clk_ecspi(0);
}
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return IMX_GPIO_NR(5, 9);
}
#endif
int board_init(void)
{
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
..
..
..
return 0;
}
In clk-imx8mp.c:
// spi clk def
static const char *imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
static const char *imx8mp_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
static const char *imx8mp_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
static int imx8mp_clk_probe(struct udevice *dev)
{
..
..
// starts here
clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300));
clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
}
It worked for us but these changes are not for production. For example when I asked for 60Mhz SPI clock, I got 40Mhz. Above clock settings may not be fully accurate. I expect fully tested accurate patch from Toradex or NXP 
I hope this helps.
Thank you.
