Verdin AM62 + Mallow Carrier Board: SPI1 DTS Configuration — Are Output Pins Correct?

[raju3003]

Hi Toradex Team,

I’m working with the Verdin AM62 SoM on the Mallow Carrier Board, and I’ve successfully built a Yocto image. I’m currently trying to enable SPI1 and have written the following device tree overlay for it:

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include "k3-pinctrl.h"

/ {
    compatible = "toradex,verdin-am62";
};

&main_pmx0 {
    pinctrl_spi1: spi1grp {
        pinctrl-single,pins = <
            AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* SPI1_CLK  - SODIMM 196 */
            AM62X_IOPAD(0x0024, PIN_INPUT, 1) /* SPI1_D0   - SODIMM 200 */
            AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* SPI1_D1   - SODIMM 198 */
            AM62X_IOPAD(0x001c, PIN_OUTPUT, 1) /* SPI1_CS0 */
        >;
    };
};

&main_spi1 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_spi1>;
    spidev@0 {
        compatible = "spidev";
        reg = <0>;
        spi-max-frequency = <3000000>;
        spi-cpol;
        spi-cpha;
        bits-per-word = <8>;
    };
};

However, I noticed that in the upstream arch/arm64/boot/dts/ti/ device trees, SPI pins are usually defined as PIN_INPUT instead of PIN_OUTPUT.

So my question is:

Is it correct to use PIN_OUTPUT for SPI1_CLK, MOSI, and CS0 in my use case?
Or should these be set as PIN_INPUT like in the upstream DTS files?

Any guidance on best practices or confirmation that this overlay is appropriate for Verdin AM62 would be greatly appreciated.

Thanks in advance!

Best Regards,
Raju

[ToradexAI]

Hi, I’m the Toradex AI Assistant. The Toradex Support team will follow up with you shortly!

Did you like my answer?

---

Hello!

For the Verdin System on Module (SoM) family, the SPI interface signals are defined as follows:

SODIMM Pin	Signal Name	Description
196	SPI_1_CLK	SPI Serial Clock (SCK)
198	SPI_1_MISO	SPI Master Input, Slave Output (DIN)
200	SPI_1_MOSI	SPI Master Output, Slave Input (DOUT)
202	SPI_1_CS	SPI Chip Select; SPI Enable Signal; SPI Slave Select

Based on these signal descriptions:

1. SPI_1_MOSI should be configured as PIN_OUTPUT since it is the Master Output.
2. SPI_1_MISO should be configured as PIN_INPUT since it is the Master Input.
3. SPI_1_CLK should be configured as PIN_OUTPUT because the module acts as the master device generating the clock signal.
4. SPI_1_CS should be configured as PIN_OUTPUT as it is controlled by the master to select the slave device.

Your pin configuration in the device tree overlay seems correct for the Verdin AM62 acting as an SPI master device.

To verify the SPI interface functionality, you can use the spidev_test utility. This tool helps ensure that the SPI interface is operating correctly:

# spidev_test -D /dev/verdin-spi-cs0
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 KHz)

I hope this helps! If you have any more questions about configuring your Toradex hardware, feel free to ask.

Best regards, Toradex AI Assistant.

[lucas_az.tx]

Hi @raju3003!

We already have an overlay if you are trying to use/test the SPI. You can find it here.

It enables the spidev to be used in userspace. For more information about it, please refer to this article.

Regarding the upstream, are you using the upstream kernel? As you are using a written device tree as an example, I would recommend using the device tree from the same branch of the kernel you are using. Otherwise, you could face errors due to the different device trees.

Best regards.
Lucas Azeituno

[raju3003]

Hi @lucas_az.tx

First of all, thank you for the response!

I’m using the same code structure you shared previously for GPIO pull-up configuration, and I followed that style to set up the spidev overlay as well.

How to Add a Custom Device Tree Overlay to Verdin AM62 Yocto Build?

Hi @raju3003! First, did you add your layer to bblayers.conf? If not, it won’t consider your modifications when building the new image. Second, your overlay isn’t correct. Please refer to this line of k3-am62-verdin.dtsi to use as an example on how you should write a node. In your overlay, you’ll need to add a node to &main_pmx0 and then change its function. Besides that, you must be sure that any other node doesn’t reserve the pin you’re trying to use and, if so, disable the node using the pi…

kernel - (6.6.84-7.2.0-devel)

Now, coming to the pre-built overlay — I see that it looks like this:

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2023 Toradex
 */

// Verdin AM62 spidev

/dts-v1/;
/plugin/;

/ {
	compatible = "toradex,verdin-am62";
};

/* Verdin SPI_1 */
&main_spi1 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	spidev@0 {
		/* Use compatible "rohm,dh2228fv" to bind spidev driver */
		compatible = "rohm,dh2228fv";
		reg = <0>;
		spi-max-frequency = <10000000>;
	};
};

Let’s say I want to modify the max frequency and SPI mode — I’d like to know where exactly I should make those changes, especially since it looks like these overlays are being pulled from GitHub directly.

Once everything is in place, what’s the best way to check if spidev is actually working?

Thanks again!

Best regards,
Raju

[lucas_az.tx]

Hi @raju3003!

As far as I understood, you can change the mode, and probably the frequency, using the spidev_test, which is the script you can use to test the spidev. You can find it here.

You’ll need to compile it with make (remember to prepare your computer for cross-compilation with arm64). Then you can copy it using scp command to the module, and run the script.

I saw it has some interesting flags, as you can see below:

Usage: ./spidev_test [-2348CDFHILMNORSZbdilopsv]
general device settings:
  -D --device         device to use (default /dev/spidev1.1)
  -s --speed          max speed (Hz)
  -d --delay          delay (usec)
  -l --loop           loopback
spi mode:
  -H --cpha           clock phase
  -O --cpol           clock polarity
  -F --rx-cpha-flip   flip CPHA on Rx only xfer
number of wires for transmission:
  -2 --dual           dual transfer
  -4 --quad           quad transfer
  -8 --octal          octal transfer
  -3 --3wire          SI/SO signals shared
  -Z --3wire-hiz      high impedance turnaround
data:
  -i --input          input data from a file (e.g. "test.bin")
  -o --output         output data to a file (e.g. "results.bin")
  -p                  Send data (e.g. "1234\xde\xad")
  -S --size           transfer size
  -I --iter           iterations
additional parameters:
  -b --bpw            bits per word
  -L --lsb            least significant bit first
  -C --cs-high        chip select active high
  -N --no-cs          no chip select
  -R --ready          slave pulls low to pause
  -M --mosi-idle-low  leave mosi line low when idle
misc:
  -v --verbose        Verbose (show tx buffer)

You can set the mode and the max speed using these flags.

Feel free to ask if you have any doubts.

Best regards.
Lucas Azeituno.