Using the UART in M4 core


We have Apalis iMX8 on Eval carrier board.

We built your “image tdx-reference-minimal-image” using bitbake and also checked your prebuilt reference image i.e. Apalis-iMX8_Reference-Minimal-Image-Tezi_5.6.0

The question is that we want to use the UART in the M4_0 core and make it available to linux applications running on the A cores.

Sorry for simple questions… I guess that:
- we need firmware in the M4_.0 to handle the UART device (not accesible to the Acores)
- further, we will need some rmsg channel to/from the M4core-Acore for sending receiving through this UART device

Can you confirm the above questions?

Looking at the settings in my u-boot, I concluded that no firmware is loaded in the M4 as I could not find any m4_0.bin file in the image and the loadm4image_0 looks imcomplete and not part of the bootcommad, is that assumption correct?

Apalis iMX8 # printenv bootcmd
bootcmd=run distro_bootcmd
Apalis iMX8 # printenv distro_bootcmd
distro_bootcmd=scsi_need_init=; for target in ${boot_targets}; do run bootcmd_${target}; done
Apalis iMX8 # printenv boot_targets
boot_targets=mmc1 mmc2 mmc0 usb0 dhcp
Apalis iMX8 # printenv m4boot_0
m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0
Apalis iMX8 # printenv loadm4image_0
loadm4image_0=${load_cmd} ${loadaddr} ${m4_0_image}
Apalis iMX8 # printenv load_cmd
Error: “load_cmd” not defined
Apalis iMX8 # printenv loadaddr
Apalis iMX8 # printenv m4_0_image

Finally are there any reference images for the M4 and linux that we can use and, ideally, make available the UART to the applications running on linux?

Thanks for your help


Hi @jotara,

Let me know if everything is clear and feel free to ask any questions you might have.

It’s not possible to share the UART between the M4 Core and the A Core. All the resources are allocated during boot time.

Instead, you will need to choose where you want to use the UART and then communicate the data using the RPMsg.
For example, if you want to use it with the M4 Core, you will need to allocate the UART inside the M4 firmware and disable it inside Linux (A core) device tree. Then, if you need to send data using the A core, you can use the rpmsg channel to send messages to the M4 Core, and M4 will handle it and send the messages through UART. So UART will only be exposed to the M4 Core.

Yes, it is correct, u-boot comes with a default name “m4_0.bin” but this file isn’t called by default. You should set the “bootaux” command to initialize the M4 core.

Please check this page: High performance, low power Embedded Computing Systems | Toradex Developer Center

There are many examples from NXP that you can find in the MCUXpresso SDK. When you download it (High performance, low power Embedded Computing Systems | Toradex Developer Center) you will see the examples folder inside your SDK.

Best Regards,

Thanks for your answer Hiago.
I do not need the M4 up an running by now, just need to use the UART in pins M40_UART0_RX and M40_UART0_TX from the A core.
My device tree is based on imx8-apalis-ixora-v1.2.dtsi, where an imx8-ss-cm41.dtsi is included. I found an
imx8-ss-cm40.dtsi in the freescale directory and included this, then enabled the M40 UART with
&cm40_lpuart {
status = “okay”;

On boot I got some error messages due to this inclusion
[ 0.374543] 000: imx8qxp-lpcg-clk 37620000.clock-controller: failed to get clock parent names
[ 0.374609] 000: imx8qxp-lpcg-clk: probe of 37620000.clock-controller failed with error -22

[ 0.391261] 004: clk: couldn’t get clock 0 for /bus@34000000/serial@37220000

I could not check in detail yet, but should I include anything else?


Hi @jotara,

Ok, I think I got it now, do you want to use the M40.UART0.RX and TX in the Cortex-A?

Unfortunately, this is not possible. This UART is only available to the Cortex M4 Core 0, as you can see in the NXP Reference Manual:


The cortex M4 features one I2C, one UART, and one GPIO coupled to the M4 cortex, therefore it is not accessible and shared with the Cortex-A. You need to choose a different UART that is available for Cortex-A. Please check the Apalis iMX8 datasheet.

Best Regards,

Thanks for your answer. That was indeed my initial understanding.
What I do not understand is what are imx8-ss-cm41.dtsi (included in your reference DT imx8-apalis-ixora-v1.2.dts) and imx8-ss-cm40.dtsi good for… as these resources/devices are not available to the A cores?

Hi @jotara,

I’m sorry, checking the imx8qp-apalis-v1.1-ixora-v1.2.dts I can see only two includes:

// SPDX-License-Identifier: GPL-2.0+ OR X11
 * Copyright 2021 Toradex


#include "imx8qp-apalis-v1.1.dtsi"
#include "imx8-apalis-ixora-v1.2.dtsi"

/ {
	model = "Toradex Apalis iMX8QP V1.1 on Apalis Ixora V1.2 Carrier Board";
	compatible = "toradex,apalis-imx8qp-v1.1-ixora-v1.2",

Can you explain to me which file includes the imx8-ss-xm40?

Best Regards,

imx8-ss-cm41.dtsi is included by imx8qm.dtsi, included by imx8qm-apalis-v1.1.dtsi. Notice that I use imx8qm not qp


Hi @jotara,

Thanks for clarifying.

The imx8qm.dtsi comes from NXP, therefore we don’t make any modifications to it. NXP includes the imx8-ss-cm40.dtsi (and cm41), it only allocates the resources for the M4 Core, but not necessarily enables it (you can check the “status” of the nodes).

Therefore I still recommend you customize your device tree (with overlays, for example) to remove these nodes from the Cortex-A to avoid any conflict between M4 and Linux.

Best Regards,