Usage of pin PCIE_1_RESET# as deep sleep wake up source

Hi,

on the Verdin AM623 chipset, I am trying to set the pin SODIMM 244 labelled as PCIE_1_RESET# as wake up source from the deep sleep mode (echo mem > /sys/power/state).

So far I had no chance to make it work. Can you please confirm if this pin as functional for this scope, and eventually share a device overlay setting example to make it work?

Thanks,

Andrea

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Deep Sleep Mode Limitations on Verdin AM62

Based on the available documentation, there are specific limitations when using GPIOs during Deep Sleep mode on the Verdin AM62 V1.2 SoM that you need to be aware of (1).

Key Deep Sleep Behavior

When the Verdin AM62 V1.2 transitions to Deep Sleep mode, the following occurs (1):

  • GPIO output buffers are disabled, placing the pins in a High-Z state
  • Internal pull-up and pull-down resistors (ranging from 15 kΩ to 30 kΩ) are automatically enabled by the SoC’s firmware
  • Output voltage on I/O pins will be affected by external load’s pull-up or pull-down values and bias currents

Pin Configuration Information

Unfortunately, the available documentation doesn’t provide specific information about SODIMM 244 (PCIE_1_RESET#) pin configuration or its wake-up capabilities from Deep Sleep mode. The pin assignment tables in the Verdin AM62 V1.2 datasheet would need to be consulted to determine the exact SoC ball mapping and alternate functions for this specific pin (2).

Device Tree Overlay Approach

For device tree overlay customization, you can reference the comprehensive guide available (3). The process typically involves:

  1. Creating a device tree overlay to configure the pin as a wake-up source
  2. Compiling the overlay using Device Tree Compiler (DTC) or TorizonCore Builder
  3. Deploying the overlay to your system

Voltage Considerations

When working with Deep Sleep mode, you should estimate the output voltage on I/O pins under worst-case conditions, considering the internal 30kΩ pull-up or pull-down resistor (1). This is crucial because voltage conflicts between internal and external pull resistors can cause unexpected peripheral behavior.

Recommendation

I’d suggest checking the complete pin assignment tables in the Verdin AM62 V1.2 datasheet to verify the exact SoC ball name and alternate functions for SODIMM 244. Additionally, you may want to consider using an I2C GPIO expander as an alternative solution for controlling peripherals during Deep Sleep state, as mentioned in the documentation (1).

Best regards, Toradex AI Assistant.

Please note that Deep Sleep mode is not supported on Verdin AM62 versions v1.0 and v1.1
Please check the Verdin AM62 errata

Hello Alex,

yes I know about this, actually I just received v1.2 board after we discovered this issue some week ago. I am doing tests and overlay configurations, but this specific pin seems not working for wake up even if it is in the pin list table in datasheet as deep sleep wake up source.

Do you have any other information related to this chip where this pin may be not usable or locked by any other peripheral that maybe I have to detach in the overlays?

Thanks,

Andrea

You need to either disable the &verdin_pcie_1_reset_hog node

&verdin_pcie_1_reset_hog {
	status = "disabled";
};

or remove the gpio property from that node

&verdin_pcie_1_reset_hog {
    /delete-property/ gpios;
};
2 Likes

Thank you Alex, I’ll try this way and let you know, eventually I’ll mark it as solution in the thread.

I have one doubt, if you could give me confirmation: in the datasheet I see that the pin is enlisted also in another table, where it is mentioned as “Reserved” and there is a note:

1 The available pin functions fulfill the pin function defined in the family specification.

Thas is marked as “No”

may this configuration interferee with the wake up mechanism, or shall I ignore this and consider this pin avaialble for my scope?

“Reserved” means that the function of that X1 pin is not defined by the Verdin family specification and may vary between different Verdin module variants—nothing more.

In the case of the Verdin AM62, this pin is routed directly to the SoC’s MCU_SPI0_CS0 ball and, in Toradex BSPs, it is muxed as MCU_GPIO0_0. No other on-module components are connected to this pin.

Therefore, you can fully rely on the official TI AM62x documentation for its behavior and usage.