Unpredictable crashes of Cortex-M7 (i.MX8MP) since moving some code and data to OCRAM

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Hi, I’m the Toradex AI Assistant.

I might make mistakes or occasionally get you wrong. Our support team will step in if needed.

Good evening Chris & Team,

Thank you for the detailed description of your OCRAM setup and the linker configuration. I’ll address your questions based on the available documentation.

Memory Areas and OCRAM on Verdin iMX8M Plus

According to the Toradex documentation, the Verdin iMX8M Plus features a heterogeneous multicore architecture with the Cortex-M7 core alongside 4 Cortex-A53 primary CPU cores(1). The system includes Tightly Coupled Memory (TCM) for the M7 core, offering low-latency access(1).

The documented memory layout for Verdin iMX8M Plus shows(1):

  • DTCM for M7: 128KB at 0x2000_0000-0x2001_FFFF
  • ITCM for M7: 128KB at 0x0000_0000-0x0001_FFFF
  • DDR Address: 2GB accessible by M7 at 0x4000_0000-0xBFFF_FFFF

Observations About Your Setup

Looking at your configuration, I notice a few points worth verifying:

  1. OCRAM Address Range: Your linker file places OCRAM at 0x20200000-0x2024FFFF. While this appears to be a valid OCRAM range for iMX8MP, the official Toradex documentation for Verdin iMX8M Plus(1) does not explicitly list OCRAM regions in the memory map table (unlike the Colibri iMX7 documentation(2)(1), which does document OCRAM regions).

  2. Linux Reserved Memory: You mentioned the memory is declared no-map in the device tree overlay. The verdin-imx8mp_hmp_overlay.dts does reserve memory regions for M7 communication(3), but you should verify that your specific OCRAM regions are properly excluded from Linux access.

  3. Cache Coherency: Your MPU configuration sets OCRAM as cacheable (write-back/write-allocate). With RemoteProc and shared memory scenarios, cache coherency between the M7 and A53 cores could be a concern if any of this OCRAM is accessed by both cores.

Recommendations

Before we can provide more specific guidance, could you clarify:

  1. Which exact version of Torizon OS are you running? (You mentioned 7.4.0 tag, but please confirm the full version)
  2. Are you using RemoteProc to start the M7 firmware?(4)
  3. Is any of the OCRAM region shared with Linux, or is it exclusively used by the M7?
  4. Have you verified the device tree overlay is correctly applied and the memory regions are properly reserved?

You can use the tdx-info command to get detailed information about your system configuration. See: Getting Device Information with Tdx-Info | Toradex Developer Center

Additional Considerations

The TCM regions can be accessed with zero wait-states and provide massively better performance than DRAM, even if cached(1). The fact that your code ran stably in TCM for 1.5 years but crashes when moved to OCRAM suggests the issue might be related to:

  • Memory access timing differences
  • Cache configuration issues
  • Potential conflicts with other system components using OCRAM
  • Memory region alignment or MPU configuration

Once you provide the additional details about your exact OS version and setup, I can offer more targeted guidance.

Best regards,
Toradex AI Assistant.

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