U-Boot splash screen - LVDS

Technical Support
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1

Hi,

I am having troubles displaying splash screen image in U-boot on custom display connected to LVDS channel A in single channel mode.

I have added below display timings to display array in u-boot/board/toradex/apalis_imx6/apalis_imx6.c:

{
	.bus	= -1,
	.addr	= 0,
	.pixfmt	= IPU_PIX_FMT_LVDS666,
	.di 	= 0,
	.detect	= detect_default,
	.enable	= enable_lvds,
	.mode	= {
		.name           = "640x240",
		.refresh        = 60,
		.xres           = 640,
		.yres           = 240,
		.pixclock       = 93457,
		.left_margin    = 32,
		.right_margin   = 29,
		.upper_margin   = 3,
		.lower_margin   = 8,
		.hsync_len      = 8,
		.vsync_len      = 2,
		.sync           = FB_SYNC_VERT_HIGH_ACT,
		.vmode          = FB_VMODE_NONINTERLACED
} }

After setting panel=640x240 environment variable in U-boot still nothing gets displayed.

I have above timings in kernel device tree so display and also kernel splash screen is working when linux is booting.

This is debug output in u-boot while starting:

Display: 640x240 (640x240)
ipu_clk = 260000000
ldb_clk = 65000000
read BS_CLKGEN0 div:0, final_rate:4160000000, prate:260000000
read BS_CLKGEN0 div:0, final_rate:4160000000, prate:260000000
IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)
mxcfb_init_fbinfo: 4 640 112 524
Framebuffer structures at: fbi=0x4df24690 mxcfbi=0x4df248a0
allocated fb @ paddr=0x4DF2A600, size=614400.
Channel already disabled 9
Channel already uninitialized 9
setup_disp_channel1 called
bpp_to_pixfmt: 16
init channel = 9
pixclock = 10700000 Hz
panel size = 640 x 240
pixel clk = 10700000Hz
setup_disp_channel2: 95ffcff 640 240 1280 4df2a600 4df75600
bpp_to_pixfmt: 16
initializing idma ch 23 @ 027005c0
ch 23 word 0 - 00000000 00000000 00000000 E0001800 0003BC4F
ch 23 word 1 - 09BEEAC0 0137CA98 20E3C000 F2C13FC0 00082CA0
PFS 0x7, BPP 0x3, NPB 0xf
FW 639, FH 239, Stride 1279
Width0 4+1, Width1 5+1, Width2 4+1, Width3 7+1, Offset0 0, Offset1 5, Offset2 11, Offset3 16
IPU_CONF =      0x000006A0
IDMAC_CONF =    0x0000002F
IDMAC_CHA_EN1 =         0x00800000
IDMAC_CHA_EN2 =         0x00000000
IDMAC_CHA_PRI1 =        0x18800000
IDMAC_CHA_PRI2 =        0x00000000
IPU_CHA_DB_MODE_SEL0 =  0x00800000
IPU_CHA_DB_MODE_SEL1 =  0x00000000
DMFC_WR_CHAN =  0x00000090
DMFC_WR_CHAN_DEF =      0x202020F6
DMFC_DP_CHAN =  0x00009694
DMFC_DP_CHAN_DEF =      0x2020F6F6
DMFC_IC_CTRL =  0x00000002
IPU_FS_PROC_FLOW1 =     0x00000000
IPU_FS_PROC_FLOW2 =     0x00000000
IPU_FS_PROC_FLOW3 =     0x00000000
IPU_FS_DISP_FLOW1 =     0x00000000
Framebuffer at 0x4df2a600
Video: Drawing the logo ...

If I try to display u-boot splash screen on HDMI it works fine, but when I change to LVDS nothing gets displayed.

Regards, Sandi Mlinar

2

This is exactly my issue at the moment, but with the Unified Display Port. It does not even turn on the backlight. There should be a file or variable in Uboot sources that’s jamming everything.

3

Yes,

We both have the same issue. Maybe the problem is in the LDB parent clock as it was in kernel version 3.14.28 …

4

The issue is isolated to UBoot. It must be something that Uboot has no access to OR misconfigured.

I just have no idea what it is at the moment.

5

I still think that this issue is related to LDB parent clock.

This thread also notes the same problem. I tried to set LDB0, LDB1 clk select to 000/000 (mxc_ccm.>cs2cdr) as stated in the thread but still no success.

6

Did you enable an option in menuconfig to get that debug info? I would like to compare it to mine so I can check my pixclk as well. Would you mind sharing which one you enabled?

7

Add

#ifndef DEBUG
#define DEBUG
#endif

in include/common.h and you’ll get debug output.

8

Here’s my debug output

Display: wvga-rgb-personalized (800x480)
ipu_clk = 260000000
ldb_clk = 65000000
read BS_CLKGEN0 div:0, final_rate:4160000000, prate:260000000
read BS_CLKGEN0 div:0, final_rate:4160000000, prate:260000000
IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)
mxcfb_init_fbinfo: 4 640 112 524
Framebuffer structures at: fbi=0x2df44690 mxcfbi=0x2df448a0
allocated fb @ paddr=0x2DF4AA40, size=1536000. 
Channel already disabled 9
Channel already uninitialized 9
setup_disp_channel1 called
bpp_to_pixfmt: 16
init channel = 9
pixclock = 33260000 Hz
panel size = 800 x 480
pixel clk = 33260000Hz
setup_disp_channel2: 95ffcff 800 480 1600 2df4aa40 2e006240
bpp_to_pixfmt: 16
initializing idma ch 23 @ 027005c0
ch 23 word 0 - 00000000 00000000 00000000 E0001800 00077C63
ch 23 word 1 - 05C00C48 00B7D2A9 20E3C000 F2C18FC0 00082CA0
PFS 0x7, BPP 0x3, NPB 0xf
FW 799, FH 479, Stride 1599
Width0 4+1, Width1 5+1, Width2 4+1, Width3 7+1, Offset0 0, Offset1 5, Offset2 11, Offset3 16
IPU_CONF =     0x000006A0
IDMAC_CONF =    0x0000002F
IDMAC_CHA_EN1 =         0x00800000
IDMAC_CHA_EN2 =         0x00000000
IDMAC_CHA_PRI1 =        0x18800000
IDMAC_CHA_PRI2 =        0x00000000
IPU_CHA_DB_MODE_SEL0 =  0x00800000
IPU_CHA_DB_MODE_SEL1 =  0x00000000
DMFC_WR_CHAN =  0x00000090
DMFC_WR_CHAN_DEF =      0x202020F6
DMFC_DP_CHAN =  0x00009694
DMFC_DP_CHAN_DEF =      0x2020F6F6
DMFC_IC_CTRL =  0x00000002
IPU_FS_PROC_FLOW1 =     0x00000000
IPU_FS_PROC_FLOW2 =     0x00000000
IPU_FS_PROC_FLOW3 =     0x00000000
IPU_FS_DISP_FLOW1 =     0x00000000
Framebuffer at 0x2df4aa40
Video: Drawing the logo ...
9

Unfortunately my LVDS panel I was using for testing somehow broke down. That said we are looking at this now.

10

This works just fine for me both in U-Boot 2016.11-toradex as well as mainline once I adjusted the PWM_BKL1 polarity. I used our former Fusion 10 inch single channel LVDS panel with the following settings:

setenv panel wsvga-lvds

Debug output as follows:

U-Boot 2016.11-00001-g33d12b0431-dirty (Dec 18 2017 - 15:13:18 +0100)

CPU:   Freescale i.MX6D rev1.5 at 792 MHz
Reset cause: WDOG
I2C:   ready  
DRAM:  512 MiB
PMIC:  device id: 0x10, revision id: 0x11, programmed
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Display: wsvga-lvds (1024x600)
ipu_clk = 260000000
ldb_clk = 65000000
read BS_CLKGEN0 div:0, final_rate:4160000000, prate:260000000
read BS_CLKGEN0 div:0, final_rate:4160000000, prate:260000000
IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)
mxcfb_init_fbinfo: 4 640 112 524
Framebuffer structures at: fbi=0x2df4d690 mxcfbi=0x2df4d8a0
allocated fb @ paddr=0x2DF536C0, size=2457600.
Channel already disabled 9
Channel already uninitialized 9
setup_disp_channel1 called
bpp_to_pixfmt: 16
init channel = 9
pixclock = 64998000 Hz
panel size = 1024 x 600
pixel clk = 64998000Hz
read BS_CLKGEN0 div:0, final_rate:1040000000, prate:65000000
setup_disp_channel2: 95ffcff 1024 600 2048 2df536c0 2e07f6c0
bpp_to_pixfmt: 16
initializing idma ch 23 @ 027005c0
IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)
ch 23 word 0 - 00000000 00000000 00000000 E0001800 00095C7F
ch 23 word 1 - 05C0FED8 00B7D4DB 20E3C000 F2C1FFC0 00082CA0
PFS 0x7, BPP 0x3, NPB 0xf
FW 1023, FH 599, Stride 2047
Width0 4+1, Width1 5+1, Width2 4+1, Width3 7+1, Offset0 0, Offset1 5, Offset2 11, Offset3 16
IPU_CONF =      0x00000660
IDMAC_CONF =    0x0000002F
IDMAC_CHA_EN1 =         0x00800000
IDMAC_CHA_EN2 =         0x00000000
IDMAC_CHA_PRI1 =        0x18800000
IDMAC_CHA_PRI2 =        0x00000000
IPU_CHA_DB_MODE_SEL0 =  0x00800000
IPU_CHA_DB_MODE_SEL1 =  0x00000000
DMFC_WR_CHAN =  0x00000090
DMFC_WR_CHAN_DEF =      0x202020F6
DMFC_DP_CHAN =  0x0000968A
DMFC_DP_CHAN_DEF =      0x2020F6F6
DMFC_IC_CTRL =  0x00000002
IPU_FS_PROC_FLOW1 =     0x00000000
IPU_FS_PROC_FLOW2 =     0x00000000
IPU_FS_PROC_FLOW3 =     0x00000000
IPU_FS_DISP_FLOW1 =     0x00000000
Framebuffer at 0x2df536c0
In:    serial
Out:   serial
Err:   serial
Model: Toradex Apalis iMX6 Dual 512MB V1.1A, Serial# 04915432
Net:   using PHY at 7
FEC [PRIME]
Hit any key to stop autoboot:  0 
Apalis iMX6 #
11

After adjusting that (which I have already did) only got access to backlight, still no logo. Is there any other thing I should lookout for? (I know im not using LVDS sorry for asking here you can answer in my question)

12

@marcel.tx

Yes but your panel has 64MHz pixelclock, mine has 10.7MHz, I think that the issue is with displays with low pixelclock…

I had the same issue with kernel 3.14.28 where setting different ldb parent clock solved the issue and it was fixed in 3.14.52.

13

I guess with such an unusually low LVDS pixel clock frequency one indeed might have to hand tune the clocking thereof.

Another issue we have seen is that if the display does honor the RESET_MOCI signal you may have to de-assert that one manually in U-Boot as well prior to getting anything on your screen.

Some displays are also rather picky if it comes down to DATA_ENABLE vs. HSYNC/VSYNC type signalling and you may have to experiment with doing either or.