Trouble enabling second network interface in official 3rd-party Android image installed on Apalis iMX8 QM module

Technical Support
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1

Hello.

My setup is the following:

Carrier board: Toradex Ixora rev. 1.1A;
Module: Apalis iMX8 QuadMax 4GB IT ver. V1.1C;
Installed software: Toradex_Apalis-iMX8_B0_Kynetics-Android-Image_10.0.0_2.3.0-eval-SNAPSHOT-20210709 with modified Device Tree

I want to know if it is possible to enable the second network interface on my current configuration?
After unpacking the “dtbo-imx8qm.img” file from the Android 10 archive, I obtained the “dt.0.src” and “dt.1.src” files:
dt.0.src (164.2 KB)
dt.1.src (164.3 KB)

What changes should be made in order to enable the second network interface?
At this moment only eth0 interface is available.

Thank you.

2

Hi @embeddedsystem,

By a second network interface, do you mean another ethernet connector?
Although it’s possible to use a second interface on Apalis iMX8:

The Apalis iMX8 features a second Ethernet port. If this port is required, an additional PHY needs
to be implemented on the carrier board. The second MAC in the SoC can provide two different
interface standards for the connection with the PHY

Ixora has only one connection to the ethernet port.

Please, let me know what exactly you want to enable and I can help you with that.

Best Regards,
Hiago.

3

I don’t know how that PHY should be written and in which structure it should be added. I tried different solutions, but none of them worked.

4

Hi @embeddedsystem,

To add another ethernet port to your Apalis iMX8, you’ll need to add a fec2 node with all the configurations for your external PHY chip. Let me show you an example:

&fec1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_fec1>;
	pinctrl-1 = <&pinctrl_fec1_sleep>;
	fsl,magic-packet;
	fsl,mii-exclusive;

	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-id";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@7 {
			compatible = "ethernet-phy-ieee802.3-c22";
			interrupt-parent = <&lsio_gpio1>;
			interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
			micrel,led-mode = <0>;
			reg = <7>;
			reset-assert-us = <2>;
			reset-deassert-us = <2>;
			reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
			reset-names = "phy-reset";
		};
	};
};

This is the fec1 node from the imx8-apalis-v1.1.dtsi. It describes the first ethernet connection port that comes with Apalis by default. Now, let’s see an example form NXP evaluation board, where they added the second ethernet port:

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_fec2_supply>;
	fsl,magic-packet;
	nvmem-cells = <&fec_mac1>;
	nvmem-cell-names = "mac-address";
	fsl,rgmii_rxc_dly;
	status = "okay";
};

This comes from imx8qm-mek.dts.

Therefore, you will need to add the fec2 node and the configurations related to your external chip. You can use the above device tree node as an example for your project.

Remember to follow the recommendation from the Apalis iMX8 datasheet:

The secondary RGMII/RMII Ethernet interface is not part of the Apalis standard. Therefore, the
signals are not compatible with other Apalis modules. Most of the signals are located on the
module edge connector pins, originally reserved as a parallel RGB LCD interface.
The secondary RGMII/RMII Ethernet interface needs special attention regarding the supply voltage
level. The RGMII/RMII voltage is switchable through LDO1OUT of the second PMIC PF8100. The
voltage level must be defined by software configuration. During the power-up sequence, the IO
voltage is set to 3.3V by default. All the RGMII/RMII signals are configured as GPIO inputs with
enabled pull-down resistors. If the interface is used with 1.8V IO voltage, it is crucial to configure
first the LDO1OUT voltage and then change the alternate function to RGMII/RMII. This ensures full
compatibility with 1.8V RGMII signal levels.
If the secondary Ethernet interface is used as RGMII, the output voltages are limited to 1.8V and
2.5V. For RMII and other alternate functions (e.g., GPIO) of these pins, also 3.3V logic level is
available. Please note that the ENET1_MDC and ENET1_MDIO are always set to 3.3V, independent
of the RGMII/RMII signals’ output voltage settings. This switchable I/O rail was introduced on V1.1
of the Apalis iMX8 module. The V1.0 is only able to output 3.3V. Please note that using the RGMII
interface at a 3.3V voltage level is not supported by the specification of the SoC and is not
recommended by NXP.

Let me know if you need anything else.

Best Regards,
Hiago.