Iam working on custom carrier board design for apalis imx8 module. As a reference iam using Ixora v1.2A carrier board with same 6 layer stackup. But referring to differential pair routing design rules put me confusion as the values set as width and gap doesn’t match the required impedance profiles… even the width and spacing with which the board is routed is different and almost matches with my calculated values. Is there any specific reason for setting constraints in Altium rules with a different values??
Got it… sorry for my mistake.
When I selected use impedance profile check box, it listed the corresponding constraints.
Perfect that your issue is solved.
Thanks for the feedback.