Technical Inquiry: Dual-Channel LVDS support for 1920x1200 on Apalis iMX6Q 2GB IT V1.1D

Technical Support
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Dear Toradex Support Team,

I am currently working with the Apalis iMX6Q 2GB IT V1.1D and am looking to validate the technical feasibility of driving a high-resolution display with the following specifications:

  • Resolution: 1920x1200 (WUXGA) @ 60Hz

  • Interface: Dual-Channel LVDS (Split-mode)

  • Required Pixel Clock: ~150 MHz

Based on the i.MX6Q SoC documentation, my understanding is that while a single LVDS channel is limited to 85 MHz, using Split-Mode across both channels should support a combined clock of up to 170 MHz, making this resolution feasible.

Could you please confirm the following:

  1. Feasibility: Does the Apalis iMX6Q 2GB IT V1.1D officially support a stable 1920x1200 resolution in dual-channel split mode?

  2. Clocking: Are there any known limitations regarding the LDB (LVDS Display Bridge) clock parent or PLL configurations when hitting the 150 MHz threshold on this specific SOM revision?

  3. Reference Timings: Do you have a recommended Device Tree snippet or specific timing parameters (porches/sync) for WUXGA panels that have been verified on your reference carrier boards (e.g., Ixora or Apalis Evaluation Board)?

  4. BSP Version: Are there any specific recommendations for the Toradex BSP version (we are currently looking at Yocto-based builds) to ensure stable dual-channel operation?

We want to ensure that the 1.1D hardware revision handles this bandwidth effectively before we finalize our carrier board routing.

Thank you for your assistance.

Best regards,

Dipin

2

Hi, I’m the Toradex AI Assistant.

I might make mistakes or occasionally get you wrong. Our support team will step in if needed.

Based on the Toradex documentation and datasheet specifications, I can address your technical inquiry about dual-channel LVDS support for 1920x1200 on the Apalis iMX6Q 2GB IT V1.1D.

Feasibility Confirmation

Yes, the Apalis iMX6Q officially supports 1920x1200 resolution in dual-channel split mode (1). According to the datasheet: “The dual-channel LVDS interface can support resolutions up to 1920x1200 @60fps (170MHz pixel clock maximum)” (1). Your required ~150 MHz pixel clock is well within this specification.

Hardware Capabilities

The Apalis iMX6 provides comprehensive dual-channel LVDS support (1):

  • Single channel limit: Up to 1366x768 pixels @60fps (85MHz pixel clock maximum) (1)
  • Dual-channel capability: Up to 1920x1200 @60fps (170MHz pixel clock maximum) (1)
  • Split-mode operation: “In dual-channel configuration, the odd bits are transmitted in the first channel and the even bits transmitted in the second channel” (1)

Configuration Options

The Apalis iMX6 supports multiple LVDS configurations (1):

  • Two single-channel LVDS displays with cloned or independent content
  • One dual-channel display for high resolution applications like your 1920x1200 requirement

Known Clock Configuration Issues

However, there are documented clock configuration challenges that you should be aware of. Recent community reports indicate potential issues with LVDS pixel clock generation on Apalis iMX6 systems (2). Users have reported that the actual pixel clock can be significantly lower than specified in device tree configurations, with measured frequencies around 54-55% of the intended clock rate (2).

BSP and Device Tree Configuration

For device tree configuration, the documentation shows that LVDS setup requires proper configuration in the device tree (3). The system supports both kernel command line configuration and device tree-based setup, with command line settings taking precedence (3).

For framebuffer configuration, use this format (3):

video=mxcfb0:dev=ldb,bpp=32

Recommendations

Given the complexity of LVDS clock configuration and the documented issues with pixel clock generation, I recommend:

  1. Thorough testing: Validate the actual pixel clock output with an oscilloscope before finalizing your carrier board design
  2. Clock source verification: Pay attention to the LDB clock parent configuration, as this has been identified as a potential issue area (2)
  3. BSP selection: Use the most recent stable BSP version that includes any available clock configuration fixes

Could you specify which BSP version and OS you’re planning to use (e.g., Torizon OS, Yocto BSP version)? This will help me provide more specific configuration guidance for your setup.

Best regards, Toradex AI Assistant.

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3

Hi @dipinkrishna!

Sorry for the delayed response.

It is technically possible, but I am not aware of anyone who has tested it. Additionally, we do not have any examples or device tree snippets for this implementation, so you would likely need to implement it yourself.

If you have issues implementing this, you can contact our partners through our Partner Network. There, you’ll find people with the necessary expertise to assist you.

Best regards.