Spidev: DMA burst length


I’m successfully using the spidev on a iMX8MM board with the BSPv5.6 to transfer data with a width of 32 bit:

The data is loaded into the TX-FIFO of the spi by the dma. But what bothers me is that only 32 of the 64 FIFO registers that the ECSPI has are used:

I can remember that with BSPv5.0 there wasn’t this behavior and a burst was 2048 bits (64 x 32 bits) long.

Best regards,