SPI with DMA or large(r) buffer?

We have the following use-case and we are not sure at the moment if this is possible using SPI:
The i.MX 8 will be connected to an FPGA which prepares sampled measurement data. This data is sent at a rate of ~ 500kS/s to the board resulting in around 25-30 Mbit/s (multiple channels incl. overhead).
The FPGA is also programmed by us and we are free on the choice of interface and we thought the easiest would be SPI, but we found the following in the datasheet:


  • Up to 60 Mbps in master mode
  • Up to 40 Mbps in slave mode
  • 32-bit x 64 deep FIFO (RX and TX)
  • Master/Slave configurable
    Logically the FPGA would be the master, as he is sending the data as soon as it is ready, but we can also use the i.MX 8 as master and poll the FPGA. Anyhow we think the 2kbit buffer could run out very quickly at our data-rate and think this will only work if the SPI bus uses DMA and continuously writes directly to the memory.

Will this be possible with the Apalis board or do you suggest something completely different?


I’m unsure if using SPI for this is possible, at least not without designing your whole system around this one bandwidth requirement to not ever loose samples.

Note that Linux as a SPI slave is an uncommon use case. I’m pretty sure that the lowlevel device driver for the LPSPI HW does not support it. I’m also not sure if the generic SPI slave support has actually arrived in the NXP downstream kernel. I personally would not use Linux as a high speed slave.

The 32-bit x 64 FIFO is part of the SPI HW and thus fixed. The HW can do DMA, but it looks like this is not yet implemented in the device-tree.

I would suggest to first analyse two other possibilities.

  1. PCIe

If you are free to choose an FPGA which can do PCI express I would connect through this.
Using PCIe should also give you compatibility between the different modules of the Apalis family.


This is a interface similar to SPI, but it can use a half duplex mode with 4 data lines, increasing the bandwidth to 4 times the clock. With the higher bandwidth you should get more time to get the data out of the FIFO, by DMA or otherwise.


Thanks for the feedback. QSPI we already thought of - will there be a driver “out of the box” with the final firmware/BSP to use it similarly to SPI?
PCIe would also be an option, as our FPGA also supports it, but we never worked with PCIe so far - could you point me to an example how we would access data over PCIe?

For PCIe you’re usually operating on blocks of memory, you can write a linux driver or use UIO and userspace application to access it. For better performance you can use DMA to copy data from the device (and even better performance can be achieved when the device is being a bus master and performing the DMA on it’s own). For 30Mbit/s you’re probably OK with UIO and mmap.
What FPGA are you using?

Hi @ChrFin00 ,

I’m currently working on a communication link between i.MX 8 and a FPGA.

I was wondering if you found more information about QSPI implementation & linux drivers ?
I want to split the 4 data lines so I can have full duplex communication at hi-speed between the two devices. At this point, any documentation can be useful to me.
The native FlexSPI / QSPI kernel driver is dedicated to NOR/NAND flash memory communication. So I want to get rid of its memory specific layer/protocole (LUT table) and use it as a common raw SPI link :slight_smile:

Any advice ?

We went with FlexSPI, but as you already noticed this is limited to MDT, but we solved that by simulating a common Flash with the FPGA and use /dev/mtdX to read/write from/to the FPGA.

HI @ChrFin00
So you moved the problem to the FPGA side :
you needed to handle the MDT frame in the FPGA.

Does the logic overhead induced reduces the data throughput a lot ?
Any difficulty with writing the FPGA code ? Did you find any “out of the box” verilog/VHDL brick ?

I need to know before I chose this interface. Thanks for your answer by the way