SPI Master Continuous Mode of the TK1

Not sure if this is the right place to ask this question, but Toradex might have a little more information about this than what’s available in the TRM.

For our application, I need a streaming SPI driver for the TK1, since the default spidev and the underlying tegra drivers don’t support a streaming mode, we developed the driver ourselves.

The TK1 TRM mentions a bit in the SPI DMA Control Register (SPI_DMA_CTL) called the CONT : Enable Continuous Mode (bit 30). While the TRM doesn’t elaborate on how it works, I assume if that bit is set, the BLOCK_SIZE field in the SPI DMA Block Size (SPI_DMA_BLK) register is ignored and the SPI keeps output-ing (in the case of SPI Master) data as long as the DMA keeps filling the FIFO.

However, I am not seeing this happening. When I setup a DMA to fill the FIFO with the SPI set to Continuous Mode, the DMA seemed to have stopped after moving about 65536 packets to the FIFO (and out of the SPI pins). Dumping the SPI Transfer Status register it seemed that the SPI was still in the “Not Ready” state, the DMA bit was still enabled, and SPI interrupt didn’t get triggered and FRAME_END bit wasn’t set, but the SPI FIFO Status showed that the TX_FIFO was full. So it seems like SPI is running, but nothing is being pushed out of the FIFO.

Is there an errata on this or any more detailed information Master Continuous mode than what the TRM mentions?

Unfortunately we do not have any experience in running the TK1 SPI IP in such a mode. Maybe somebody else on the community has some further suggestions?