SPI, ~CS glitches

Technical Support
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1

Hi,
I detected glitches on the ~CS line of the SPI interface.
Some times the ~CS is accidently set low by the driver which fools the slave system.

[upload|W7toQWQRmilG7VnRrkYIhMD9TmE=]
I do a data integrity check after receiving 504 DWORDs, if there is an error the signal GH_DBGB is set for a short time. I triggerd the scope on rising edge of this signal and set the trigger point at the center of the screen to see whats happen just before and just after this error.

We can see, that the DL_~CS line is low instead of high before he error occures.

Lets take a closer look
[upload|JbKbU1zl1alF7hT7kVcpjpfIYFE=]

The DL_~CS line goes high at the end of the n-1 transfer, but than accidently goes low again. Just before the n-th transfer starts it goes high again and than low. Together with the level changes of the DL_SCLK line the slave system is fooled and sends wrong data.

With best regards

Gerhard

3

Did you try with latest release of the imx7 images? We toggle CS driving it as a GPIO and this should prevent it from unexpected toggling due to power-off of the SPI controller.
Do you have other devices connected to that same SPI using different chip-selects?