The SPI clock in mode 3 does not work correct. Expected is clock polarity high and active edge positive. After each 8 bit, the SPI Clock is set to low again:
We have an AD7793 connected to this SPI clock and have now troubles with the communication, because of this addition edges. (Because of historical reason, we can’t use CS.)
This is what our AD7793 expects:
I have also checked the SPI clock of the PXA320 and it was exactly the SPI signal the AD7793 needs.
Because we run out of PXA320, we don’t have time to develop an new hardware and really need this bug fixed in the SpiLpi.lib for the iMX6. We need at least an additional spi mode for a spi clock, so it behaviors like the spi driver of PXA320.