SPI chip select through GPIOs - Apalis iMX8

Hello,

After success enabling multiple chipselect for an SPI on apalis iMX8 (Apalis iMX8 SPI multiple chip select - Toradex Community),
I noticed that there is a relative big latency of about 35µs between selecting the chip and SPI transfer as well as after SPI transfer.
1945-3spl.png
Is there some way to reduce this big latency? this latency does not exist when using native SPI chip select pins.
I think using gpio pins seperated as chip select would be even faster than integrating them in the SPI dev, which makes enabling multiple chip select on device tree not very useful in (semi) real-time applications.

Best regards,
Majd

Hi @majd.m

I think that this is by design and there is no easy way for you to decrease this latency. You could however, try to improve the lpspi driver in drivers/spi/spi-fsl-lpspi.c. This one is tightly coupled to drivers/spi/spi.c where you can see how and when gpio gets set.
In an OS like Linux I wouldn’t necessarily say 35us is slow. Linux is built to be extremely adaptive/generic and this introduces some latency on the other hand, but as I said you’re free to improve the lpspi driver in that regards.

Best regards,
Philippe

Hi @pymenow,
Most probably yes.

Thanks @majd.m , were you also able to improve the driver for better Linux performance as indicated above ?

Will the same SPI work on the M4 using free RTOS and have far less latency ? (IMX8)

Actually, I didnt work on it. I expect this won’t be stright forward to solve anyway.

I used the gpiod library to check any difference, but it was the same issue.