A bit of an update on my previous comment.
I’ve since done some additional testing, and have found a few interesting things. Firstly, I’m now able to set (via the spidev driver) an SPI frequency of up to 40MHz. The actual frequency (as measured on an oscilloscope) is ~38MHz. This 38MHz ‘real’ frequency is observed for spidev driver speed_hz values of 30MHz to 40MHz.
Per this post, I had set the assigned-clock-rates device tree value to 128MHz (as shown above), however when checking the kernel clock configuration via cat /sys/kernel/debug/clk/clk_summary | grep spi2 I get the following:
root@apalis-imx8:~# cat /sys/kernel/debug/clk/clk_summary | grep spi2
spi2_clk 0 0 0 120000000 0 0 5000
spi2_lpcg_clk 0 0 0 120000000 0 0 5000
spi2_lpcg_ipg_clk 0 0 0 120000000 0 0 5000
I was expecting the listed frequencies to be 128MHZ (as per the device tree and the above referenced post) as opposed to the 120MHz shown. I’m not sure if this is relevant/useful information or not, but I thought I’d point it out.
This post outlines the two-stage divider used by the SPI subsystem. Applying this logic to either the 128MHz or 120MHz source clock, I’m not sure how the resultant ‘real’ SPI frequency is ~38MHz. At this stage I’m aiming to achieve a ‘real’ SPI frequency as close to 50MHz as possible (the limit of the remote processor). This may be the ~38MHz frequency I’m observing, but as I can’t make sense of this value I’d like to make absolutely certain that a frequency closer to 50MHz definitely isn’t possible.