I have an ADC conected to the SAI5 (I2S_2) interface and I’m able to get samples from it using the s/pdif receiver driver up to 64 kHz, which needs roughly a 24 MHz clock, but need to record at 128 kHz. The SAI5 interface has been configured using the .dts files, with its clock configured at 49.152 MHz, as shown below:
I don’t have the schematic, but the following table shows the connections:
ADS1278 Signal
iMX8M Mini
Function
MUX
CLK/SCLK
SODIMM 42
I2S_2_BCLK
MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK
FSYNC
SODIMM 44
I2S_2_SYNC
MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC
DOUT1
SODIMM 48
I2S_2_D_IN
MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0
Just to clarify, the CLK/SCLK from the ADC is driven using the I2S_2_BCLK (the bitclock) signal of the board, the FSYNC of the ADC with the SYNC signal and DOUT1 is the output of the ADC sent to the board as I2S_2_D_IN.
This is working for up to 64 kHz, so the connections are ok. Also, using a logic analyzer shows the correct output for both I2S_2_BCLK and I2S_2_SYNC, and as I2S_2_D_IN is the only input, there’s no need for the ADC to test the configuration.
Running arecord with the --dump-hw-params shows that it should work up to 192 kHz.
RATE = SYNC, and we are recording 8 channels, 24-bit resolution, so BCLK = 24 * 8 * RATE
And also arecord command works properly, generating desired wav output files.
For example, using: $ arecord -D hw:0,0 -r 64000 -V mono -vvv -c 8 -f S24_LE -t wav test_8ch-64ksps.wav -d 10
We measured the following signals: CH1=BCLK and CH2=SYNC (a little noisy, but it works)
In this case: 24 * 8 * 96000 = 18432000, but is fails to generate that rate.
The same happens at 128000 and 192000, and also other standard rates like 44100 and 48000.
While asking for supported hardware parameters, it shows that 192000 should be supported.
Could be a limitation on SAI5 clock source?
Do you know if a higher frequency clok source could be selected to be used by SAI5?
Thanks in advance.
At Verdin iMX8MM datasheet we have seen that SAI5 max sampling rate is 384KHz/32-bit, that it is equivalent to a bit clock of 12.288.000Hz. This max bit clock in our case limits the sample rate to 64KHz because we are using 192-bit frames.
So we have disabled NAU8822 codec in Verdin DEV board, to allow using SAI2 with our ADC.
As shown in table, SAI2 should support bit clock frequencies up to 24.576.000Hz, allowing us to use 128KHz sampling rate. But then, we noticed that the driver does not support 128KHz.
So, we tried other standard sampling rates that are supported by the driver, like 88.2KHz and 96KHz, but we get the same error:
As you can see, it fails when it tries to obtain required BCLK.
The same happens when trying multiple frequencies of them, like 44.1KHz and 48KHz.
After that we tried to change assigned-clock-rates value at &sai2 node at dts, in order to set a value to match exactly the required bit clocks, but it seems it is not capable to generate those values.
When we use the following value for 44.1KHz and 88.2KHz, that should work with a BCLK of 16.934.400Hz:
Is there a simple way to change audio_pll1_out or audio_pll2_out clock values?
I think that asigning a multiple value of 18432000Hz (96000x192) or 16934400Hz (88200x192) and then set this pllx as base of SAI2, it should be able to generate required rates.
Example: current clock value for audio_pll2_out is 361267200 Hz. How can I change it to 387072000Hz?
