Context
As part of our product validation we run repeated cold-power-cycle testing on our hardware — a custom carrier built around the Toradex SMARC iMX95 module. Through that testing we identified an intermittent cold-boot failure that we’ve traced to the module’s early boot, and we’re documenting it here in case it’s a known issue.
Environment
- Module: Toradex SMARC iMX95 Hexa, module revision V1.1A (PN 00961100)
- i.MX95 silicon: rev 2.0 (B0)
- BSP: 7.6.1 — same symptom also present on 7.5.0
- Boot firmware (OEI / System Manager / SPL) is stock Toradex; our only boot-side change is the debug instrumentation described below, which was present during the fault and is not on the path that hangs.
- Custom carrier board (no Toradex dev carrier in this setup).
Symptom
On a cold power cycle, roughly 1 in 20 boots the module comes up completely dead — no console, no network, no signs of life — and stays dead until the next power cycle, after which it boots normally. Warm reboots are not affected. This is long-standing and predates our recent BSP work.
How we localized it
Our carrier does not route the stock U-Boot console UART, so we had no early serial visibility. To instrument the early boot we added GPIO boot-stage markers: four SMARC GPIOs driven high at successive boot stages using raw GPIO MMIO writes (no dependency on the driver model, SCMI, or clocks — so they fire even if those subsystems are stuck). Highest pin still high = last stage reached.
- Marker 1 — SPL board_init_f entry (first A55 SPL C code)
- Marker 2 — SPL spl_board_init
- Marker 3 — U-Boot proper board_early_init_f (pre-relocation)
- Marker 4 — U-Boot proper board_init (post-relocation)
On every good boot, the markers light in sequence as expected.
Result (reproduced, n = 3)
On a hung cold boot, all four markers stay dark — including marker 1 (SPL board_init_f entry). The A55 SPL never executes any C code. This places the hang before the A55 is released, in the M33 boot chain (ROM → ELE → OEI/DRAM training → System Manager). We have now caught this three times (at cold cycles #45, an overnight run, and #19); all three faults show the identical all-dark signature, and no fault has ever shown even marker 1. Fault rate is consistent with the ~1-in-20 we see in normal operation.
What we’ve ruled out
- A55 SPL / U-Boot — never reached on a fault.
- Our BSP / software — symptom present on both 7.5.0 and 7.6.1.
- Carrier-side power into the SMARC connector — VDD_IN and the power/reset sequencing into the edge connector measure clean.
Question
Is this a known intermittent cold-boot behavior on the V1.1A module revision?